RISC-V virtual memory support

[knilaks...@gmail.com]

For the RISC-V core I have developed a MMU with L1 unified TLB.My ultimate aim is to boot the RISCV 32I OS.The RISCV core has Atomic instruction supported L1 Cache.I have limited idea on further proedure.The implementation is similar to this block diagram.

1.Do I need to separate the TLB for data and instruction?

2.Do I need to stick any method for TLB eviction?

3.Any specific way to integrate MMU with Cache memory?

I'm newbie to the OS related things

4.When creating the root image of RISCV 32I, I was asked to chose lot of parameters which I have no idea about.Where can I learn to understand the OS and hardware interface.Currently I'm learnig to undestand the Linux Kernel.Does this to be specific to RISCV?