Strange PLIC behaviour in Rocket-Chip

[Muhammad Ali Akhtar]

Using Rocket-Chip Multi-HART config and Sifive PLIC implementation.

I have a bare metal adapted from sifive example-plic-baremetal-multicore 

I initialize the PLIC configuration for all HARTs. All HARTS are successfully processing interrupts. However, after some time, in my interrupt service routine, I disable the PLIC interrupts only for Hart 0, But All HARTs stop processing the interrupts. 

I disable the interrupts by writing 0 to PLIC address 0x002000 and 0x002080 corresponding to both contexts for HART 0. All the rest of HARTs are still enabled to process interrupts from PLIC. But All HARTS stop external interrupt processing after writing 0 to all 32 bits of address   0x002000 and 0x002080

Any ideas? Thoughts?
Muhammad Ali Akhtar

[Tommy Murphy]

> interrupt processing after writing 0 to all 32 bits of address 0x002000 and 0x002080

You don't say how many harts you have in your design but aren't register offsets 0x2000 and 0x2080 the enable registers for harts 0 and 1 respectively?

* https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#2-memory-map

* https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#5-interrupt-enables  

* https://github.com/sifive/example-plic-baremetal-multicore/blob/c0f2fe691145f64a5b0ff7b831c55b25d5a3ae95/example-plic-baremetal-multicore.c#L86 

I think you need to explain more clearly the nature of your target/setup, what you're trying to do and what exactly is not working as expected.

[Muhammad Ali Akhtar]

Thanks Tommy for the response. 

I have 4 HARTS in my config. 

Here is my understanding of HARTs and PLIC address space. 

Each HART has 2 contexts / modes. Machine mode / Super Visor. mode. In baremetal environment, SuperVisor mode is irrelevant 

0x2000 HART 0 Context 0

0x2080 HART 0 Context 1

Muhammad Ali Akhtar

[Tommy Murphy]

> I have 4 HARTS in my config. 

> 0x2000 HART 0 Context 0

> 0x2080 HART 0 Context 1

The code that you're using says this:

```

#define PLIC_HART0_ENABLE_BASE_ADDR 0x0

#define PLIC_HART1_ENABLE_BASE_ADDR 0x80

```

implying that the hart0 enable is at offset 0x0 and the hart1 enable is at offset 0x80.

And it only mentions 2 harts so it's unclear how that code is dealing with 4.