Hi Ruslan,
Thanks! These are both small Microcontroller class rv32im cores with
embedded static RAM. Each core has private hardware multiply and
divide, interrupt controller, SPI, I2C, UART, GPIO and timer peripheral
and debug capability. The NanorRisc5 uses a simple APB like bus and has
256K combined code/data SRAM, the ETH-Zurich core uses an AXI bus and
has 256K code + 128K data SRAM.
Both cores have arbitrated shared access to the ASIC peripherals (ADC,
DAC, memory capture controllers, PAD control, etc.). Plus the I/O for
peripherals for each can be muxed to the GPIO and programmable
peripheral IO (PIO) pins. Each has dedicated UART RX/TX pins to allow
simultaneous printf statements / debugging.
Additionally, the ETH-Zurich core has direct AXI bus access to the
embedded 2 ADC capture and 1 DAC playback SRAM blocks (1.8M Byte total).
Ken