14nm RISC_V cores alive!

Skip to first unread message

Ken Pettit

Oct 15, 2017, 2:39:25 PM10/15/17
to hw-...@groups.riscv.org

At IQ-Analog, we received our first ever GF 14nm ASIC test chip a couple
of weeks ago and assembled evaluation boards containing the chip this
past Thursday. After a bit of a slow startup, we were able to download
and execute code yesterday via JTAG to both the NanoRisc5 (in-house
grown picorv32 variant with debug spec 0.9 debugging added) and the
ETH-Zurich versions of the RISC-V cores!

While we have not bought up the 1GHz clock source yet to test full speed
operation (1 GHz for NanoRisc5, 500 Mhz for ETH-Zurich), we have been
able to conduct these initial tests using a slower 200 MHz "debug clock
input" path. We still have a lot of things to bring up and test on this
ASIC, but I wanted to share the news of working RISC-V cores in 14nm and
extend a thank you to everyone in the RISC-V community for developing
the RISC-V architecture and intrastucture.


Ruslan Bukin

Oct 15, 2017, 2:50:06 PM10/15/17
to Ken Pettit, hw-...@groups.riscv.org

What extensions are supported by this ASIC? Also does it have memory controllers?


> --
> You received this message because you are subscribed to the Google Groups "RISC-V HW Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+un...@groups.riscv.org.
> To post to this group, send email to hw-...@groups.riscv.org.
> Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.
> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/59E3AB57.8090601%40gmail.com.

Ken Pettit

Oct 15, 2017, 3:18:53 PM10/15/17
to Ruslan Bukin, hw-...@groups.riscv.org
Hi Ruslan,

Thanks! These are both small Microcontroller class rv32im cores with
embedded static RAM. Each core has private hardware multiply and
divide, interrupt controller, SPI, I2C, UART, GPIO and timer peripheral
and debug capability. The NanorRisc5 uses a simple APB like bus and has
256K combined code/data SRAM, the ETH-Zurich core uses an AXI bus and
has 256K code + 128K data SRAM.

Both cores have arbitrated shared access to the ASIC peripherals (ADC,
DAC, memory capture controllers, PAD control, etc.). Plus the I/O for
peripherals for each can be muxed to the GPIO and programmable
peripheral IO (PIO) pins. Each has dedicated UART RX/TX pins to allow
simultaneous printf statements / debugging.

Additionally, the ETH-Zurich core has direct AXI bus access to the
embedded 2 ADC capture and 1 DAC playback SRAM blocks (1.8M Byte total).


Ruslan Bukin

Oct 15, 2017, 3:31:29 PM10/15/17
to Ken Pettit, hw-...@groups.riscv.org
Looks interesting, and set of devices look good too.
Hope it become available on market so people can buy it eventually.


Muhammad Ali Akhtar

Oct 15, 2017, 11:52:50 PM10/15/17
to Ruslan Bukin, Ken Pettit, hw-...@groups.riscv.org
congratulations! ken,

can you share more implementation details (if they are not confidential)  like.

eda tools used for P&R, STA, signoff, 
chip area, packaging

Muhammad Ali Akhtar
Principal Design Engineer

Edmund Humenberger

Oct 16, 2017, 5:05:38 AM10/16/17
to RISC-V HW Dev
Dear Ken,

Clifford Wolf (the author of picoRV32) will be in the Bay Area for most of November. Would be cool to meet and talk about your experience
using picoRV32.

Would be also cool to talk about formal Verification of designs:

Are you interested? if yes, please get in contact with me at edmund at symbioticeda dot com


PS: I am business partner of Clifford Wolf in the www.symbioticeda.com startup.
Reply all
Reply to author
0 new messages