Reason to select ADD for NOP and MV?

[Valentin Nechayev]

hi,

This is more of a historic interest but could suggest something
principal about the core design groundings.
According to the ISA spec:
- MV (well, copying) between registers is translated into: addi rd, rs, 0.
- NOP is translated into: addi x0, x0, 0.

My question is: why addi and not ori or xori?
If the maximum simplest design is implemented without decoding of
these special cases, "add" involves a summator which scheme is more
expensive in execution - more gates for each bit, cross-bit carry
chains, maybe more clocks to execute.

In the basic spec I see the following:

> ADDI was chosen for the NOP encoding as this is most likely to take
> fewest resources to execute across a range of systems (if not
> optimized away in decode).

But this is not fully correct, all bitwise operations require even fewer
resources.

> Also, an ADDI functional unit is more likely to be available in a
> superscalar design as adds are the most common operation.

But, in a superscalar design, explicit decoding of NOP and MV is
required anyway (with register renaming, MV is translated into another
alias for the same physical register).

Is there something not explained in spec?


-netch-

[Krste Asanovic]

First, if a machine optimizes NOPs at decode, it doesn’t really matter which opcode is picked as long as it’s easy to decode.

If a machine doesn’t optimize NOPs at decode, you’d want to choose something which will likely have the most available execution resources.

ADDs are the most common operation, especially if you include the adds in memory offset calculations.
Designing a machine such that logic operations took less cycles than adds probably means you were optimizing the wrong thing.
Even in very slow machines with tiny resources.

Krste

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