set up intelliJ as the RocketChip generator's IDE

[Jerry Ho]

I already followed the README to clone the whole repository and the corresponding sub-module. And I wonder if I can set up the intelliJ to work as the IDE. 

 After importing the repo into intelliJ,  I run sbt compile under the root directory, and it worked without error. But when I type sbt run, it will give errors like "there are multiple main class, you should use runMain",  more importantly, the project inside intellij can not resolve very basic symbols like "sbt". 

I felt confused about this, I knew running  cd emulator &  make will generate the verilog file, but I thought the "make" command actually call the sbt run, I wonder where I can get the specific calling parameters? And also,  how can I set up the intellij as the IDE, so that I can make life much much much more easier? 

[FangFei Yang]

http://blog.edmondcote.com/2018/04/using-intellij-as-rocketchip-ide.html 

[Jerry Ho]

I followed the instructions in that post, But, when I rebuild the project using the intellij, there are a lot of errors:

/////////////////////////////////////////////////////////////////////////

all {file:/home/jerry/rocketchipGen/newRocketIntellij/}core/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}core/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}chisel/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}chisel/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}rocketchip/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}rocketchip/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}docs/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}docs/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}api-config-chipsalliance/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}api-config-chipsalliance/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}hardfloat/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}hardfloat/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}macros/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}macros/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}rocket-macros/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}rocket-macros/test:products

[warn] Multiple main classes detected.  Run 'show discoveredMainClasses' to see the list

[info] Compiling 3 Scala sources to /home/jerry/rocketchipGen/newRocketIntellij/target/scala-2.12/test-classes ...

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:7:15: object testutils is not a member of package firrtl

[error] import firrtl.testutils.{FirrtlMatchers, FirrtlPropSpec}

[error]               ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:12:46: not found: type FirrtlPropSpec

[error] class LintConflictingModuleNamesSpec extends FirrtlPropSpec with FirrtlMatchers {

[error]                                              ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:12:66: not found: type FirrtlMatchers

[error] class LintConflictingModuleNamesSpec extends FirrtlPropSpec with FirrtlMatchers {

[error]                                                                  ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:30:3: not found: value property

[error]   property("It should emit LintViolations for conflicting DesiredNameAnnotations") {

[error]   ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:55:24: value should is not a member of Seq[Set[String]]

[error]     conflictingModules should be (Seq(Set("Bar_1", "Bar_2")))

[error]                        ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:55:31: not found: value be

[error]     conflictingModules should be (Seq(Set("Bar_1", "Bar_2")))

[error]                               ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:58:3: not found: value property

[error]   property("It should catch LintViolations not fixed by with RenameDesiredNames") {

[error]   ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:82:24: value should is not a member of Seq[Set[String]]

[error]     conflictingModules should be (Seq(Set("Bar_1", "Bar_2")))

[error]                        ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:82:31: not found: value be

[error]     conflictingModules should be (Seq(Set("Bar_1", "Bar_2")))

[error]                               ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:85:3: not found: value property

[error]   property("RenameDesiredNames should be able to fix LintViolations") {

[error]   ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:109:24: value should is not a member of Seq[Set[String]]

[error]     conflictingModules should be (Seq())

[error]                        ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/linting/rule/LintConflictingModuleNamesSpec.scala:109:31: not found: value be

[error]     conflictingModules should be (Seq())

[error]                               ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:7:15: object testutils is not a member of package firrtl

[error] import firrtl.testutils.{FirrtlMatchers, FirrtlPropSpec}

[error]               ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:19:38: not found: type FirrtlPropSpec

[error] class RenameDesiredNamesSpec extends FirrtlPropSpec with FirrtlMatchers {

[error]                                      ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:19:58: not found: type FirrtlMatchers

[error] class RenameDesiredNamesSpec extends FirrtlPropSpec with FirrtlMatchers {

[error]                                                          ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:54:25: value should is not a member of Seq[freechips.rocketchip.transforms.naming.StableNameAnnotation]

[error]         currStableNames should be (stable)

[error]                         ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:54:32: not found: value be

[error]         currStableNames should be (stable)

[error]                                ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:55:27: value should is not a member of Seq[freechips.rocketchip.transforms.naming.UnstableNameAnnotation]

[error]         currUnstableNames should not be (unstable)

[error]                           ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:55:34: not found: value not

[error]         currUnstableNames should not be (unstable)

[error]                                  ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:60:3: not found: value property

[error]   property("It should rename modules if it can and ignore strategies which fail to result in unique names") {

[error]   ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:103:25: value should is not a member of firrtl.ir.Circuit

[error]     outputState.circuit should be (Parser.parse(check))

[error]                         ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:103:32: not found: value be

[error]     outputState.circuit should be (Parser.parse(check))

[error]                                ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:107:74: value should is not a member of Seq[firrtl.annotations.Annotation]

[error]     outputState.annotations.filterNot(_.isInstanceOf[DeletedAnnotation]) should be (Seq(

[error]                                                                          ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:107:81: not found: value be

[error]     outputState.annotations.filterNot(_.isInstanceOf[DeletedAnnotation]) should be (Seq(

[error]                                                                                 ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:114:3: not found: value property

[error]   property("It should keep modules names stable between runs") {

[error]   ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:169:3: not found: value property

[error]   property("It should error if renaming to an already existing module name") {

[error]   ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:189:5: not found: value an

[error]     an [Exception] should be thrownBy renameNames(testCase)

[error]     ^

[error] /home/jerry/rocketchipGen/newRocketIntellij/src/test/scala/transforms/naming/RenameDesiredNamesSpec.scala:189:27: not found: value be

[error]     an [Exception] should be thrownBy renameNames(testCase)

[error]                           ^

[error] 28 errors found

[error] (Test / compileIncremental) Compilation failed

[error] Total time: 4 s, completed Sep 13, 2020, 9:13:13 PM

[IJ]sbt:rocketchip> 

///////////////////////////////////////////

sames that all problems happened in the firrtl module, i have no idea why the firrtl is not an subproject of chisel. Instead it publishLocal, and then chisel can use it. Can you further clarify this? thanks

[FangFei Yang]

Open firrtl in another intellij, compile and publishlocal there.

In not sure if the followings are necessay:

You may also need to change sbt related settings in Settings > build, execution, deployment > build tools > any

Change sbtlaunch to sbt-launch.jar in your local project and choose "use sbt shell" for imports and for builds.

[Nasir Khan]

I am stuck in the same problem. can generate verilog code in my own established chisel project but can not compile rocket core in  intelliJ . i have followed that link to but unable to compile. Once resolved please do post the solution or make a comprehensive tutorial of it. thanks in advance.  

[Jerry Ho]

I create another intellij project and import the firrtl subdirectory as the source, and set the sbt as you specified.  then  I type clean & publishLocal in the sbt shell in the intellij, it indicated that the publish has been successful:

  

published rocketchip_2.12 to /home/jerry/.ivy2/local/edu.berkeley.cs/rocketchip_2.12/1.2-SNAPSHOT/poms/rocketchip_2.12.pom

[info]  published rocketchip_2.12 to /home/jerry/.ivy2/local/edu.berkeley.cs/rocketchip_2.12/1.2-SNAPSHOT/jars/rocketchip_2.12.jar

[info]  published rocketchip_2.12 to /home/jerry/.ivy2/local/edu.berkeley.cs/rocketchip_2.12/1.2-SNAPSHOT/srcs/rocketchip_2.12-sources.jar

[info]  published rocketchip_2.12 to /home/jerry/.ivy2/local/edu.berkeley.cs/rocketchip_2.12/1.2-SNAPSHOT/docs/rocketchip_2.12-javadoc.jar

[info]  published ivy to /home/jerry/.ivy2/local/edu.berkeley.cs/rocketchip_2.12/1.2-SNAPSHOT/ivys/ivy.xml

[success] Total time: 301 s (05:01), completed Sep 13, 2020, 8:49:37 PM

---------

then I close the intellij, reopen the whole rocket project,  but when i rebuilt the whole project using Build->Rebuild Project, the exactly same error occured. 

I noticed that if i click the rebuild project button, it actually executed the  following 

all {file:/home/jerry/rocketchipGen/newRocketIntellij/}api-config-chipsalliance/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}api-config-chipsalliance/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}core/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}core/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}chisel/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}chisel/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}macros/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}macros/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}hardfloat/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}hardfloat/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}rocket-macros/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}rocket-macros/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}rocketchip/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}rocketchip/test:products {file:/home/jerry/rocketchipGen/newRocketIntellij/}docs/products {file:/home/jerry/rocketchipGen/newRocketIntellij/}docs/test:products

what i felt confused for most is that why the firrtl module is not regarded as a dependency, instead it is used by chisel subproject as a locally published module. 

can you give me some suggestion on the next move, thanks !

[Hogege NaN]

Hi

"there are multiple main class, you should use runMain"

This is not problem on IntelliJ, check warning message on sbt that gives same message as warning.

The error message means that there are multiple main classes in your project.

I think you do runMain then the sbt checks root class in the project. When it detects multiple of that, it generates such message.

You need to read tutorial.

Best,

S.Takano

2020年9月14日(月) 15:45 Jerry Ho <jerry...@gmail.com>:

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[Jerry Ho]

Thanks for the replying, but I get the error even when i just build(intellij Build-> Build the project) the project, I thought the run task wont be involved in the build process.

Also, even when I type "show discoveredMainClasses" in the sbt shell, it said there are 3 main:

[info] * freechips.rocketchip.groundtest.Generator

[info] * freechips.rocketchip.system.Generator

[info] * freechips.rocketchip.unittest.Generator

I used "runMain freechips.rocketchip.groundtest.Generator" (I wonder if this is the right syntax to choose one of the main class to execute?), but it went this :

[warn] Multiple main classes detected.  Run 'show discoveredMainClasses' to see the list

[warn] Multiple main classes detected.  Run 'show discoveredMainClasses' to see the list

[info] running freechips.rocketchip.groundtest.Generator 

------------------------------------------------------------------------------

Error: Exactly one top module required

Try --help for more information.

------------------------------------------------------------------------------

Exception: sbt.TrapExitSecurityException thrown from the UncaughtExceptionHandler in thread "run-main-3"

[error] Nonzero exit code: 1

[error] (Compile / runMain) Nonzero exit code: 1

[error] Total time: 2 s, completed Sep 14, 2020, 12:49:22 AM

I wonder what I should do to execute a specific main class.

[Hogege NaN]

I do not know the intelij, but at SBT;

>set ‘runMain package_name_of_main.your_runmain_name’

Can order top class, intelij indeed have same.

Best,

S.Takano

2020/09/14 16:52、Jerry Ho <jerry...@gmail.com>のメール:

[FangFei Yang]

Hi, 

TL;DR

delete test folder inside rocketchip's src directory and rebuild (may need to restart sbt)

That has nothing to do with main class.

What's happening: 

For some reason, RocketChip's developers decide to use some code inside Firrtl's tests in RocketChip's tests. Because I'm working on an old code so I didn't notice that.

When compiled with makefile, this was achieved by ... simply just compile & copy the compiled firrtl_2.12-tests.jar to .. I think "test_lib" and it seems that their sbt script will find and add it to classpath. You can look into Makefrag for more detail..

However, for building with sbt, since we publishLocal manually, the test.jar 

1. won't build => this can be solved easily by changing "publishArtifact in Test := false," to "publishArtifact in Test := true," in firrtl/build.sbt
2. won't include in rocketchip's build.sbt => sorry I tried to manually add it as "  libraryDependencies ++= Seq("edu.berkeley.cs" %% "firrtl" % "1.3-SNAPSHOT" % "test")," in build.sbt but it won't work. I'm not very familar with sbt's building system so maybe there is something wrong.. I can confirm that sbt do try to find firrtl_2.12-tests.jar after adding this, but it just not showing in the classpath..

So, the workaround is clear... since all we want to do is to use IDE, we can simply DELETE the whole test folder inside src directory and everything will work smoothly. 

It should be fine.. although I'm not sure what might happen to makefile.. but now you can build and run inside intellij IDEA.

Best Regards,

Fangfei Yang

[Nasir Khan]

Dear FangFei Yang do you have run and build rocket chip in intellij IDEA or can you do a try on it. if you have already implemented it before please make a step by step tutorial or consolidate the previous tutorial  http://blog.edmondcote.com/2018/04/using-intellij-as-rocketchip-ide.html 

I am new to scala and intellij IDEA i tried for 2 weeks but still unable to achieve the same. building rocket chip in intellij IDEA. Any body who achieve running Rocket chip in intellij IDEA please show this black magic art to us too. thanks in advance to all. i will try myself again on weekend too.

[FangFei Yang]

Hi guys,

I made this video https://www.youtube.com/watch?v=BhKz8umpILg about setting up the intellij. It takes youtube sometime to transcode the video.. and I havn't edited the video so it contained some trash clips that is just compiling... But the steps are the same.. somehow publishLocal the firrtl, then do whatever you can to build rocketchip.. 

Best Regards,

Fangfei Yang

[Jack Koenig]

Hi all,

I apologize for my delay in responding. I was hoping that the pull request I'm about to describe would be done already so I could swoosh in and tell you there's a better way, but I'm not quite done with it yet. In any case, here's what's going on:

The issue you're running into is that traditionally we struggled to get the firrtl source dependency to work with chisel3 in the rocket-chip flow, so we had this Make/SBT hybrid that would build a firrtl fat jar (firrtl + all of it's dependencies in 1 jar) and put it in the SBT unmanaged directory (rocket-chip/lib) so that SBT would load the class files from there. The approach of publishing FIRRTL locally also works, but has the downside of being global to the user, so it affects all rocket-chip workspaces if you happen to be working on more than 1.

This flow has always been bad, and while it's been possible (if awkward) to get IntelliJ working, other IDE flows like Scala Metals don't work at all.

As part of bumping to Chisel 3.4*, I also improved the SBT build flow so that not only will it include firrtl in the same SBT build when building from source, it'll also be possible to easily switch to using the published versions of chisel3 and firrtl instead of building from source. I also [mostly] fixed the SBT flow for Scala Metals, so it should be relatively straightforward to use IntelliJ or any other IDE with rocket-chip. The branch is still WIP so please don't rely on it yet, but you can keep tabs on its progress here: https://github.com/chipsalliance/rocket-chip/pull/2617

*Still in the process of being released, 3.4.0-RC2 should be out in the next few days with lots of improvements over RC1

~Jack

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/44f25b73-9b19-41e2-a65e-27166eb62644n%40groups.riscv.org.

[Jack Koenig]

Hello everyone,

Rocket Chip has an improved build flow as part of the Chisel 3.4 bump that I just merged. It should be *much* easier to use it with an IDE, with only 1 minor thing to tweak. This is described in the README: https://github.com/chipsalliance/rocket-chip#-building-rocket-chip-with-an-ide

Please let me know if you have any questions or issues!

~Jack

[Nasir Khan]

Thanks for your update. as Fangfei Yang has already pointed out in his video we can use intellij IDE as development IDE but for building use the terminal. It still not working in building from within the intellij IDE but using the terminal works fine. And yes now it setup easily as compared to previous.  Thanks for the support.