ECALL EBREAK and MRET

[xhayd]

Hello Everyone !!

I was going through the privileged and the system aspects of the RISC-V ISA and came across instructions like ECALL, EBREAK and MRET and URET (from the user spec v2.1 and the priv spec v1.9.1). I need clarification on these instructions

ECALL => the spec says " the instruction is used to make a request to the supporting execution environment which is usually an Operating System. The ABI for the system will define how parameters for the environment request are passed but usually these will be in defined locations in the register file" I`am not able to make sense of this statement from a hardware point, what exactly happens in the hardware when an ECALL is fetched and decoded, what happens in the execution stage, does it read the IRF and generate some signal or modifies some value in a CSR register.

EBREAK => the spec says " the instruction is used by debuggers to cause control to be transferred back to a debugging environment" , would this mean that upon encountering EBREAK the control should jump to a subroutine that reads all the registers in the cpu, Iam not able to get a hang of what this would do in hardware

MRET, URET => the spec says that these are used to return after handling a trap. there are separate trap return instructions for each privilege mode. Does MRET help in returning after handling a machine mode trap, if yes, then lets consider that there are 2 modes implemented in a processor viz. Machine and User mode. The cpu boots up in machine mode and then there is a mode change from M to U mode, now it is running user mode software, lets say now if a trap occurs (assume the cpu does not support user mode trap handling ) the mode changes from user to machine mode and once in machine mode the trap is handled, once the trap handler is executed we can have a MRET at the end (the last instruction) of the trap handler that upon execution changes the mode to User mode and starts executing the user mode code again.

Would like to know if this understanding is correct.

also I would like to know how the privilege mode change occurs, is it through an instruction, or by updating some value in a CSR or through some other mechanism that is completely in the hardware and not in the software space.

It would be really helpful if someone could shed some light on these doubts :-)

Thanks !!

[Stefan O'Rear]

On Tue, Apr 25, 2017 at 5:41 AM, xhayd <xha...@gmail.com> wrote:
> Hello Everyone !!
>
> I was going through the privileged and the system aspects of the RISC-V ISA
> and came across instructions like ECALL, EBREAK and MRET and URET (from the
> user spec v2.1 and the priv spec v1.9.1). I need clarification on these
> instructions
>
> ECALL => the spec says " the instruction is used to make a request to the
> supporting execution environment which is usually an Operating System. The
> ABI for the system will define how parameters for the environment request
> are passed but usually these will be in defined locations in the register
> file" I`am not able to make sense of this statement from a hardware point,
> what exactly happens in the hardware when an ECALL is fetched and decoded,
> what happens in the execution stage, does it read the IRF and generate some
> signal or modifies some value in a CSR register.
>
> EBREAK => the spec says " the instruction is used by debuggers to cause
> control to be transferred back to a debugging environment" , would this mean
> that upon encountering EBREAK the control should jump to a subroutine that
> reads all the registers in the cpu, Iam not able to get a hang of what this
> would do in hardware

https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/uNE1WL8svXs/vjy1AuN8FAAJ

> MRET, URET => the spec says that these are used to return after handling a
> trap. there are separate trap return instructions for each privilege mode.
> Does MRET help in returning after handling a machine mode trap, if yes, then
> lets consider that there are 2 modes implemented in a processor viz. Machine
> and User mode. The cpu boots up in machine mode and then there is a mode
> change from M to U mode, now it is running user mode software, lets say now
> if a trap occurs (assume the cpu does not support user mode trap handling )
> the mode changes from user to machine mode and once in machine mode the trap
> is handled, once the trap handler is executed we can have a MRET at the end
> (the last instruction) of the trap handler that upon execution changes the
> mode to User mode and starts executing the user mode code again.
>
> Would like to know if this understanding is correct.

MRET works as you have described, yes. (URET is not used in the
normal flow; it's a placeholder name for a future extension.)

-s