Programming RISC-V with jtag

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sajjad ahmed

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Mar 24, 2021, 12:26:36 PMMar 24
to RISC-V HW Dev
Hello everyone!
I need guidance on how can we program our RISC-V cpu using jtag interface.
and if anyone have gdb guide for performing system bus access using RISC-V debug module so, please guide me.

Regards
Sajjad Ahmed

Tommy Murphy

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Mar 24, 2021, 12:51:50 PMMar 24
to sajjad ahmed, RISC-V HW Dev
Since you don't provide any specific information about the nature of your RISC-V target, debug hardware or debug implementation all I can suggest is that you look at the following:

(1) the RISC-V debug spec: https://github.com/riscv/riscv-debug-spec
(2) the OpenOCD RISC-V fork (kindly worked on mainly by SiFive): https://github.com/riscv/riscv-openocd
(3) existing RISC-V debug implementations such as these: https://gist.github.com/brabect1/a39c5470b4cf49524919bfb3e3f20a5c , https://github.com/pulp-platform/riscv-dbg , (and I'm sure that there are others).

Hope this helps
Cheers
Tommy

sp...@section5.ch

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Mar 25, 2021, 4:53:34 AMMar 25
to RISC-V HW Dev, tommy_...@hotmail.com, sajjad.a...@gmail.com
Do you already have an In Circuit Emulation ('ICE') feature implemented in HW? There are different ways to do it (Vendors often roll their own, esp when it comes to FPGAs). Once you have that, you just feed opcodes to your target via JTAG (what a proxy like OpenOCD or gdbproxy does when connecting via gdb).
There's also a virtualized debug TAP (test access port via ICE) found in my in-house setup (https://section5.ch/index.php/2019/10/24/risc-v-in-the-loop/) which you can spin in a virtual machine (Docker container) and access/test the co-simulated HW via Python scripts. However this is very lean & mean, doesn't follow the rather complex official RISC-V spec and should only serve as example on how to do basic ICE.
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