Random test for hardware

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Suseela Budi

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Sep 2, 2016, 9:12:43 AM9/2/16
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Can any one suggest a formal verification or any random test generator of riscv ISA?
I want to check my hardware with all the corner cases.

Clifford Wolf

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Sep 2, 2016, 9:25:33 AM9/2/16
to Suseela Budi, RISC-V HW Dev
riscv-torture [1] is a generator for small test programs.

For PicoRV32 [2] I'm also using csmith [3] to generate random C programs that I
run on PicoRV32. The scripts for that can be found here [4]. A writeup
how it works can be found at the end of this [5] thread.

I would recommend using this technique in addition to riscv-torture, in
part because it has much better coverage of the compressed ISA.

[1] https://github.com/ucb-bar/riscv-torture
[2] https://github.com/cliffordwolf/picorv32
[3] https://embed.cs.utah.edu/csmith/
[4] https://github.com/cliffordwolf/picorv32/tree/master/scripts/csmith
[5] https://github.com/ucb-bar/riscv-torture/issues/7

Sebastian Bøe

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Sep 2, 2016, 9:56:07 AM9/2/16
to Clifford Wolf, Suseela Budi, RISC-V HW Dev

I copied Clifford's technique of using Csmith for randomized testing
and can attest that it is easy to set up and quickly finds bugs that
are missed by riscv-tests and "run Linux and hope everything
works"-based testing ...

scripts: https://github.com/SebastianBoe/turborav/tree/v0.3.0/hw/src/test/csmith


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Andreas Olofsson

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Sep 2, 2016, 2:03:23 PM9/2/16
to Sebastian Bøe, Clifford Wolf, Suseela Budi, RISC-V HW Dev
My 2 cents...neither the risc-torture or the cmith are sufficient for use in product silicon. (not random enough and has clear coverage holes). This is especially critical for super optimized micro architectures and custom RTL implementations where corner cases tend to pop up (despite the risc-v architecture being clean and orthogonal). Apologies if I misunderstood the torture code, but it doesn't seem like it's completely random, but instead based on pre determined sequences? This might be ok for a simple pipeline, but as soon as you start having deep pipelines and exceptions, nasty bugs will pop up that are sequence dependent (and demand complete randomization).

In my opinion (based on many product tapeouts) the probability of building bug free silicon without true random verification is VERY low. You can get to something that is pretty clean without having high quality DV and there might not even be any "killer bugs", but the support burden associated with a length errata sheet of annoying little bugs could easily kill profitability and success of the chip.

Having a high quality random DV environment should be a priority for building trust in the risc-v architecture and associated RTL implementations. 

Here's a pointer to the what we did for Epiphany (open source GPL DV code based on systemC libraries). Not sure if it's usefeul to anyone, but wanted to point to it in case anyone is interested in building a random test generator for risc-v. The basic idea is to crate legal tests that completely randomizes EVERYTHING (regs, values, memory locations, instructions, sequence, options, etc) and use machine power to get the coverage. This approach has served the industry well for 20 years with tools like (specman, SystemVerilog, etc). We didn't have the money for a lot of tools back in 2008 so we went the open source root based on systemc libraries. 


Andreas
 






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Shubhodeep Roychoudhury

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Sep 5, 2016, 12:18:22 AM9/5/16
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I have not evaluated riscv-torture or csmith before, but, we at Valtrix Systems develop an EDA tool called STING which can be used for the functional verification of CPU/SoC implementations. Any architectural/micro-architectural feature can be validated with sufficient ease using the different testing paradigms supported in the tool.

Feel free to contact me in case you are interested in more details.

Truong Giang

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Oct 31, 2020, 4:05:10 AM10/31/20
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Currently I am also doing this task in university, could you suggest output sequences for me?

Vào lúc 20:12:43 UTC+7 ngày Thứ Sáu, 2 tháng 9, 2016, bsl.rg...@gmail.com đã viết:
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