Tilelink spec query: 9.4. TL-UL and TL-UH Messages on Channel A and D

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Asutosh Mishra

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May 19, 2023, 1:57:03 AM5/19/23
to RISC-V HW Dev

Hi,

We have few doubts on Tilleink spec. We are not sure where to raise our queries. Please help us redirecting to proper POC.

 

9.4. TL-UL and TL-UH Messages on Channel A and D

In addition to new messages, TL-C specifies implied permission transfers for these existing messages from TL-UL and TL-UH.

  1. Get implicitly Cap the permissions as None (Invalid).
  2. {PutFullData, PutPartialData, ArithmeticData, LogicalData} implicitly Cap the permissions as not Read+Write [Trunk] or [Tip], i.e. as None [Invalid] or Read [Branch].

 

From above section of the spec, we understand if a data block is already acquired and the TL-UH command is tried from one Core (i.e. M1) then it affects the permission of the Cache attached to M1.

Queries:

  1. Suppose we have Acquired a block, then send Get for that block. As per my understanding if a data block is Acquired, with at least with Read permission and assuming this access is not released then that Master/Core should not get Read miss and so should not send Get command further. So in which case this scenario might arise? Please confirm whether my understanding correct?
  2. With sending Transfer Access command from Master to Slave, does the permission automatically updated or any additional Probe command needed? Because as specified in spec the permission is capped.
  3. Does it impact other Cores as well? If yes how would slave conveys? Does it send Probe command?
  4. If we send PutFullData after a Acquire message with Read+Write permission, then the permission can be reduced to None or Read only. How we decide which permission to achieve? Who decides it whether Master or Slave?

 

Regards,

Asutosh

Tommy Murphy

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May 19, 2023, 2:49:16 AM5/19/23
to Asutosh Mishra, RISC-V HW Dev
> We have few doubts on Tilleink spec. We are not sure where to raise our queries. 

Asutosh Mishra

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Jun 1, 2023, 4:53:24 AM6/1/23
to RISC-V HW Dev, tommy_...@hotmail.com
Hi Tommy,
I have posted my query in https://github.com/chipsalliance/tilelink/issues/5 more than 2 weeks, but not got any response yet. Do you have any idea on the raised issue or any one I can reach out?

Regards,
Asutosh

Tommy Murphy

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Jun 1, 2023, 4:59:39 AM6/1/23
to Asutosh Mishra, RISC-V HW Dev
> I have posted my query in https://github.com/chipsalliance/tilelink/issues/5 more than 2 weeks, but not got any response yet. Do you have any idea on the raised issue or any one I can reach out?

Sorry, I don't, unfortunately.
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