Trivial floating point implementation in SystemVerilog

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May 12, 2021, 2:27:28 AMMay 12
to RISC-V HW Dev
Is there a trivial (combinatorial, non synthesizable) floating point implementation in SystemVerilog?
I need just a placeholder so I can run riscv_arch_test, to test my instruction decoder.
In the C extension, there are many sequences which map into either F or I, depending on XWIDTH. And i would like to make sure I decoded the right instruction.

Iztok Jeras

Krste Asanovic

May 12, 2021, 10:33:05 AMMay 12
to iztok.jeras, RISC-V HW Dev
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