Dhrystone performance and RISC -V tests results of my implementation of RV32 processor on FPGA

[vithurson subasharan]

Following are the results of the RV32I  processor implementation on Artix 7 AC701 FPGA of a 12 stage pipelined design and can run arround 130 MHz on the FPGA , This project going to get continued for upcoming years and extension and frequency improvement are going to get carried on. We are using pure verilog code(not using any fpga specific IPs) to implement the design such that it can be ASIC compatible. We need to get feedback in order to have an idea of where we are at, specially comments on the performance and a rough idea on the frequency it can go when we fabricate the design . Any feedbacks and suggestions  will be greatly helpful.

Thank you.

add..OK
addi ..OK
and..OK
andi ..OK
auipc..OK
beq..OK
bge..OK
bgeu ..OK
blt..OK
bltu ..OK
bne..OK
j..OK
jal..OK
jalr ..OK
lb..OK
lbu..OK
lh..OK
lhu..OK
lui..OK
lw..OK
or..OK
ori..OK
sb..OK
sh..OK
sll..OK
slli  ..OK
slt..OK
slti ..OK
sra..OK
srai ..OK
srl..OK
srli ..OK
sub..OK
sw..OK
xor..OK
xori ..OK

Dhrystone Benchmark, Version 2.1 (Language: C)

Program compiled without 'register' attribute

Please give the number of runs through the benchmark:
Execution starts, 100 runs through Dhrystone
Execution ends

Final values of the variables used in the benchmark:

Int_Glob:              5
        should be:    5
Bool_Glob:           1
        should be:    1
Ch_1_Glob:          A
        should be:    A
Ch_2_Glob:          B
        should be:    B
Arr_1_Glob[8]:       7
        should be:     7
Arr_2_Glob[8][7]:    110
        should be:    Number_Of_Runs + 10
Ptr_Glob->
  Ptr_Comp:          114844
        should be:   (implementation-dependent)
  Discr:                 0
        should be:     0
  Enum_Comp:      2
        should be:     2
  Int_Comp:          17
        should be :   17
  Str_Comp:          DHRYSTONE PROGRAM, SOME STRING
        should be:    DHRYSTONE PROGRAM, SOME STRING
Next_Ptr_Glob->
  Ptr_Comp:          114844
        should be:   (implementation-dependent), same as above
  Discr:                 0
        should be:    0
  Enum_Comp:     1
        should be:    1
  Int_Comp:         18
        should be:   18
  Str_Comp:         DHRYSTONE PROGRAM, SOME STRING
        should be:   DHRYSTONE PROGRAM, SOME STRING
Int_1_Loc:            5
        should be:    5
Int_2_Loc:           13
        should be:   13
Int_3_Loc:           7
        should be:   7
Enum_Loc:          1
        should be:   1
Str_1_Loc:           DHRYSTONE PROGRAM, 1'ST STRING
        should be:    DHRYSTONE PROGRAM, 1'ST STRING
Str_2_Loc:           DHRYSTONE PROGRAM, 2'ND STRING
        should be:    DHRYSTONE PROGRAM, 2'ND STRING

Number_Of_Runs: 100
User_Time: 55354 cycles, 40825 insn
Cycles_Per_Instruction: 1.355
Dhrystones_Per_Second_Per_MHz: 1806
DMIPS_Per_MHz: 1.027 (1.393 at 1 CPI for R32I)

[Sober Liu]

Hi,

What’s the gcc version for the toolchain? Someone mentioned it affects the score quite a lot.

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[vithurson subasharan]

riscv_group@entc35:~/Desktop/risc_v_latest$ gcc --version
gcc (Ubuntu 5.4.0-6ubuntu1~16.04.5) 5.4.0 20160609
Copyright (C) 2015 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

riscv_group@entc35:~/Desktop/risc_v_latest$ riscv64-unknown-elf-gcc --version
riscv64-unknown-elf-gcc (GCC) 7.1.1 20170509
Copyright (C) 2017 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

[Sober Liu]

Thanks for the info. Looks like it’s a good score for rv32 with DMIPS 1.393.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/0771f3e8-bd36-4d9b-8c49-3fb0dc8f5828%40groups.riscv.org.

[Palmer Dabbelt]

You should get ~325 instructions per loop on RV32IMC systems, and ~300 per loop
on RV64IMC systems. A, F, and D don't matter, and C has a minimal effect if
any.

I just tagged a riscv-gnu-toolchain release that gets good Dhrystone
performance. There will eventually be a blog entry about this... :).

On Tue, 07 Nov 2017 23:10:25 PST (-0800), sob...@nvidia.com wrote:
> Thanks for the info. Looks like it’s a good score for rv32 with DMIPS 1.393.
>
> From: vithurson subasharan [mailto:vith...@gmail.com]
> Sent: Wednesday, November 08, 2017 2:54 PM
> To: RISC-V HW Dev <hw-...@groups.riscv.org>
> Cc: vith...@gmail.com
> Subject: Re: [hw-dev] Dhrystone performance and RISC -V tests results of my implementation of RV32 processor on FPGA
>
> riscv_group@entc35:~/Desktop/risc_v_latest$ gcc --version
> gcc (Ubuntu 5.4.0-6ubuntu1~16.04.5) 5.4.0 20160609
> Copyright (C) 2015 Free Software Foundation, Inc.
> This is free software; see the source for copying conditions. There is NO
> warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
>
> riscv_group@entc35:~/Desktop/risc_v_latest$ riscv64-unknown-elf-gcc --version
> riscv64-unknown-elf-gcc (GCC) 7.1.1 20170509
> Copyright (C) 2017 Free Software Foundation, Inc.
> This is free software; see the source for copying conditions. There is NO
> warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
>
>
> On Wednesday, November 8, 2017 at 8:54:20 AM UTC+5:30, soberl wrote:
> Hi,
> What’s the gcc version for the toolchain? Someone mentioned it affects the score quite a lot.
>

[vithurson subasharan]

my case is RV32I , I have attached my test files , it would be great if you can have a look, you just need to run the emu.py inside the debug folder...

thank you

[vithurson subasharan]

[Palmer Dabbelt]

I won't have time to run anything, can you just send a commit log of a single
inner loop iteration?