Using the verilog(freechips.rocketchip.system.DefaultConfig.v) in rocket-chip - vsim - generated-src

[Chinmaya Dash]

Hi RISC-V HW Developers,

This is my first post here. So as a quick introduction: I would say that I have good digital design experience. I had university courses on Processors and have designed simple processor core. I am new to processor SoC designs.

I am trying to understand Rocket-Chip so that I will be able to customize it, eventually to make it a part of a product idea we are evaluating.

I have the https://github.com/freechipsproject/rocket-chip set up with me.

I jumped straight to the generated verilog with Default configuration. I don't have vcs license; I took the verilog for implementation on to Xilinx Vivado. Following queries are from my implementation attempt-

1. plusarg_reader:

There are multiple instances of plusarg_reader module. The definition is missing. I commented it out for my implementation. What does this block do? 

plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader (.out(plusarg_reader_out) ); 

2. module 'AsyncResetReg' not found

I defined this module. As the name says, I defined a D flipflip with synchronous enable and asynchronous reset. However as another discussion is going on - https://groups.google.com/a/groups.riscv.org/forum/?utm_medium=email&utm_source=footer#!msg/hw-dev/Am1dN06FCns/_oxu0DX8BAAJ

It seems resets are synchronous. Can you please clear the confusion here.

3. While synthesizing the ram-

reg [63:0] ram [33554431:0]

vivado complained that -

ERROR: [Synth 8-354] integer overflow when computing array size [src/freechips.rocketchip.system.DefaultConfig.behav_srams.v:248]

I have reduced the size by half and address bits by 1.

Any comments on this?

4. module 'SimDTM' not found

What is this module for?

The top module in generated-src is TestHarness. Is it a module that contains testbench?

My current top is 'ExampleRocketSystem'.

Other than the rocket wrapper tile there are many blocks. What is the best way for me to understand these blocks?

Any help is highly appreciated.

Regards

Chinmaya

[Kimura Masayuki]

Hi, 

plusarg_reader.v and AsyncResetReg.v is at ./vsrc directory.

And, my understanding is that Rocket Chip generated file in emulator directory is only for verilog simulation.

and we have to replace behavior RAMs defined in "freechips.rocketchip.system.DefaultConfig.behav_srams.v" into SRAM or BlockRAM.

By default, behav_srams.v is generated due to FIRRTL options that is convert Chisel description into Verilog.

If you change following Makefile, you can avoid to generate behave_sram.v instead of default memory.

- emulator/Makefrag-verilator:

 %.v %.conf: %.fir $(FIRRTL_JAR)

        mkdir -p $(dir $@)

-       $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf -faf $*.anno -ffaaf

+       $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog

For your convenience, I recommend you can use fpga-zynq repository (https://github.com/ucb-bar/fpga-zynq) for FPGA implementation.

This repository also includes "rocket-chip" as subrepository. But relatively old design is used.

I succeeded to synthesize from rocket-chip directory but my feeling is that it is little bit hard to implement on FPGA from "native" rocket-chip repository.

Thanks.

Masayuki Kimura

2017年11月25日(土) 13:09 Chinmaya Dash <chinmaya...@gmail.com>:

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[Chinmaya Dash]

Thanks a lot Masayuki.
I see that all files required for behavioral simulation are present in vsrc directory.

I can compile the ExampleRocketSystem top module.
However the TestHarness top gives me errors as there are some libraries that need to be linked.
[The source of problem is that I built the RocketChip in ubuntu enviornment in one computer and I am trying to get simulations going on in another computer where I have Cadence licenses by copying over files and directories].

I have a more general request.
To start with I want to be able to execute a small 'internal register addition' c-code on the processor.
What steps should I do?
I will actually put it as another query.

Thanks
Chinmaya

[Ghada Dessouky]

Hi,

So I am also now running into the same "integer overflow" error for the memory when synthesizing the SRAM - how did you eventually fix that?

Best,

Ghada

[Frederick HONG]

Hi Masayuki,

Maybe you could elaborate on how do you synthesize the verilogs generated from rocketchip? And how do you replace the behav_sram.v? Any details? Really appreciate it!

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[穿山羊]

I wan to run a simulation on vivado. But I got all "X's".  Did you met the same problem?