Books (please check if there are newer editions):https://www.amazon.ca/RISC-V-Reader-Open-Architecture-Atlas/dp/0999249118https://www.amazon.ca/Computer-Organization-Design-RISC-V-Interface/dp/0128122757/ref=sr_1_1?dchild=1&keywords=computer+organization+and+design&qid=1624961870&s=books&sr=1-1
Verilator is a great and fast SystemVerilog simulator, used my many (most) CPU design projects.
While it covers a larger part of the SV language than Icarus, it has limitations and some learning curve.
Not all language constructs can be synthesized into hardware, in other words, they are not in the RTL subset of the language.
Use a free synthesis tool like Xilinx Vivado, Altera Quartus or an open source tool like Yosys for synthesis,
expect errors in need of fixing.
Include build scripts and instructions in README.md files in the Git repository, it makes it easier to return to the project after taking some time off. It also makes it easier for others to help you with specific issues.
I had a quick glance at the code, it looks average, or good for a beginner.
You can use arrays and $readmemh() to load code into ROM.
It is good to have some reference to compare against, there are some online simulators available, there are also good offline simulators, but I am not sure which one to recommend.