How to generate the Verilog file for Instruction cache

[Srishti Sharma]

I am new to rocket chip generator and RISC-V and have to specifically work on the cache part of the rocket core.I am using a MacOS with IntelliJ ide and can not figure out how to test the cache and generate a Verilog file.

[Tommy Murphy]

Might be worth asking that question here, assuming that it's not already dealt with?

* https://github.com/chipsalliance/rocket-chip/discussions

* https://github.com/chipsalliance/rocket-chip/issues