Hi All,
I have some doubts about how physical memory protection works for peripherals connected to RISC-V processor cores.
For example, if there is an accelerator that access the main memory directly (potentially through DMA), are Physical Memory Attributes (PMAs) and Physical Memory Protection (PMP) rules applicable for these accesses?
My understanding was that PMAs and PMP checks should be implemented in the RISC-V core for any load/store operations from the core.
However, if this is the case, direct memory accesses from peripherals will not go through PMAs and PMP checks.
If we have peripherals that has direct access to memory, how can we implement PMAs and PMP such that memory is protected from these accesses?
I am going through the PMA and PMP description in the privileged spec but I did not see the answer to these specific questions.
Really appreciate it if you can help me to understand this better.