Memory protection for peripheral memory accesses in RISC-V

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Chathura Niroshan

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Nov 8, 2022, 12:06:33 PM11/8/22
to RISC-V HW Dev
Hi All,

I have some doubts about how physical memory protection works for peripherals connected to RISC-V processor cores.
For example, if there is an accelerator that access the main memory directly (potentially through DMA), are Physical Memory Attributes (PMAs) and Physical Memory Protection (PMP) rules applicable for these accesses?

My understanding was that PMAs and PMP checks should be implemented in the RISC-V core for any load/store operations from the core.
However, if this is the case, direct memory accesses from peripherals will not go through PMAs and PMP checks.
If we have peripherals that has direct access to memory, how can we implement PMAs and PMP such that memory is protected from these accesses? 

I am going through the PMA and PMP description in the privileged spec but I did not see the answer to these specific questions.

Really appreciate it if you can help me to understand this better. 

Greg Chadwick

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Nov 10, 2022, 6:16:11 AM11/10/22
to Chathura Niroshan, RISC-V HW Dev
Ultimately this is a system architecture question and RISC-V doesn't constrain your systems architecture (though evolving platform specifications could do in the future). The existing RISC-V architecture also doesn't really constrain how you implement PMAs, see it more as giving guidance of terminology to use and PMA types you may wish to implement.

So for a DMA engine you can do things as you please, it could obey the same PMAs some hart is obeying, it could have an entirely different set. It could mirror the PMP configuration from some hart, it could have its own set of PMP registers or something else entirely,

You could also implement an IOMMU, which there is a work in progress RISC-V specification for: https://github.com/riscv-non-isa/riscv-iommu

Kind Regards,
Greg Chadwick

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Chathura Niroshan

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Nov 14, 2022, 9:31:30 AM11/14/22
to RISC-V HW Dev, g...@lowrisc.org, RISC-V HW Dev, Chathura Niroshan
Thanks Greg, this was helpful! I will take a look at IOMMU.
I know Rocket, BOOM and Black Parrot RISC-V designs implement some PMAs.
Are there any other open-source RISC-V systems that implement PMAs?

Best regards,
Chathura
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