How to understand CSRs and find Cycles per Instruction?

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Yan

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Jun 21, 2021, 6:42:25 AMJun 21
to RISC-V HW Dev

I have a RISC-V Virtual Prototype and there are some softwares in it. I ran one of the software on RV32I and got the following report.
1, Are they CSRs or interger registers, whats the relation between them?
2, Which information indicates the Cycles per Instruction?

the report I got:
Info: /OSCI/SystemC: Simulation stopped by user.
=[ core : 0 ]===========================
simulation time: 220580 ns
zero (x0) = 0
ra (x1) = 10238
sp (x2) = 1ffffec
gp (x3) = 21990
tp (x4) = 0
t0 (x5) = 2010000
t1 (x6) = 0
t2 (x7) = 1
s0/fp(x8) = 0
s1 (x9) = 0
a0 (x10) = 0
a1 (x11) = 0
a2 (x12) = 449
a3 (x13) = 0
a4 (x14) = 0
a5 (x15) = 0
a6 (x16) = 1
a7 (x17) = 5d
s2 (x18) = 0
s3 (x19) = 0
s4 (x20) = 0
s5 (x21) = 0
s6 (x22) = 0
s7 (x23) = 0
s8 (x24) = 0
s9 (x25) = 0
s10 (x26) = 0
s11 (x27) = 0
t3 (x28) = 0
t4 (x29) = 1
t5 (x30) = 8800
t6 (x31) = 5
pc = 101f4
num-instr = 6440

Tommy Murphy

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Jun 21, 2021, 7:23:04 AMJun 21
to RISC-V HW Dev, Yan
The registers listed are integer registers.
Apart from num-instr.
I don't know what that is.
I wonder if it's something proprietary calculated by your target?

The RISC-V specs explain all of the integer registers and CSRs.
Have you read those?


From: Yan <weiyan...@gmail.com>
Sent: Monday, June 21, 2021 11:42:25 AM
To: RISC-V HW Dev <hw-...@groups.riscv.org>
Subject: [hw-dev] How to understand CSRs and find Cycles per Instruction?
 
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Yan

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Jun 21, 2021, 8:11:15 AMJun 21
to RISC-V HW Dev, tommy_...@hotmail.com
hi Tommy,

thanks for your respond. I have read the Volume 1, Unprivileged Spec v. But I confused about the chapter 10 Counters. I don't know where can I find the value of cycle,time, and instret.

I didn't calculate something. My main function is used to print some strings such as ''hello world''. And there is a entry.S file:
.globl _start
.globl _reset_vector
.equ SYSCALL_ADDR, 0x02010000

trap_handler:
    li   t0, SYSCALL_ADDR
    csrr t1, mhartid
    sw   t1, 0(t0)
    csrr t0, mepc
    addi t0, t0, 4
    csrw mepc, t0
    mret

_reset_vector:
la t0, trap_handler
csrw mtvec, t0
j _start

Makefile:
all : main.c entry.S
    riscv32-unknown-elf-gcc main.c entry.S -o main -march=rv32i -mabi=ilp32 -Wl,-e_reset_vector
    
sim: all
    riscv-vp main
    
dump-elf: all
    riscv32-unknown-elf-readelf -a main
    
dump-code: all
    riscv32-unknown-elf-objdump -D main
    
clean:
    rm -f main

I got the result after using
$make
$make sim

Tommy Murphy

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Jun 21, 2021, 8:30:24 AMJun 21
to RISC-V HW Dev, Yan
I'm still not clear on what exactly you're asking but if it's how to see the CSRs in the debugger (gdb) have you tried printing the relevant CSRs? For example

p/x $mcycle
p/x $minstret

From: Yan <weiyan...@gmail.com>
Sent: Monday, June 21, 2021 1:11:15 PM

To: RISC-V HW Dev <hw-...@groups.riscv.org>
Cc: tommy_...@hotmail.com <tommy_...@hotmail.com>
Subject: Re: [hw-dev] How to understand CSRs and find Cycles per Instruction?
 

Nelson Ribeiro

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Jun 21, 2021, 9:10:50 AMJun 21
to Yan, RISC-V HW Dev
Hi.

Maybe you should start by clarifying which tool is exactly that "RISC-V Virtual Prototype" that you mention in your first post.

Note that RISC-V internal registers and instructions are standardized, but many details of actual implementations of are not. 

It seems to me that you are using a simulator, and how to print the info that you want  (cycle,time, and instret) is something that you should ask to the authors of that tool, or to someone that knows that tool (looking to your makefile I see a 'riscv-vp main' and many of us w'ont know which tool is that...).



Yan

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Jun 21, 2021, 9:48:09 AMJun 21
to RISC-V HW Dev, ngrr.ribeiro, RISC-V HW Dev, Yan
I got the above results by running the step 3) Compile and run some Software.
I don't how can I know the number the cycles per instruction (CPI) from  the above running report.
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