openOCD connection failing at examine statge

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sajjad ahmed

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Mar 9, 2021, 4:37:55 PMMar 9
to RISC-V HW Dev

Hello everyone!
I am trying to connect RISCV debug module using jtag on verilator and this is the issue i am facing anyone can guide me what is the possible cause of this.

Warn : `riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead. force hard breakpoints
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : Initializing remote_bitbang driver
Info : Connecting to localhost:44853
Info : remote_bitbang driver initialized
Info : This adapter doesn't support configurable speed
Info : JTAG tap: riscv.tap tap/device found: 0x04f5484d (mfg: 0x426 (Google Inc), part: 0x4f54, ver: 0x0) Info : datacount=2 progbufsize=8
Error: unable to halt hart 0 Error: dmcontrol=0x80000001
Error: dmstatus =0x00000c82
Error: Fatal: Hart 0 failed to halt during examine()
Warn : target riscv.tap.0 examination failed
Info : starting gdb server for riscv.tap.0 on 3333
Info : Listening on port 3333 for gdb connections

Tommy Murphy

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Mar 9, 2021, 5:15:43 PMMar 9
to sajjad ahmed, RISC-V HW Dev
Error: unable to halt hart 0 Error: dmcontrol=0x80000001

Obviously this is the problem but without more info about your simulated debug target it's difficult to comment on why the debug module is failing to halt the hart.

A verbose OpenOCD log (using -d) might shed more light on exactly what OpenOCD is trying and failing to do here.

BTW what version of OpenOCD are you using and where did you get it? My recollection is that riscv set_prefer_sba was deprecated a long time ago so you may be using an outdated version of OpenOCD?

sajjad ahmed

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Mar 10, 2021, 1:38:22 AMMar 10
to RISC-V HW Dev, tommy_...@hotmail.com, sajjad ahmed
I have attached the output of openocd with -d flag. I am using version 0.11.0-rc2  (2021-03-04) of openocd, it was compiled from riscv-openocd repo. i had set the riscv set_prefer_sba option in the cfg file of openocd, hence the error.
log.txt

Tommy Murphy

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Mar 10, 2021, 4:09:40 AMMar 10
to sajjad ahmed, RISC-V HW Dev
OK - I don't think that it gives much more info.
The debugger is asking the target hart to halt (line 155 of the log) and then polls it waiting for that to happen but, after repeated polls, it never happens and OpenOCD gives up (line 940).
So it may be something in your target that is the problem here.
You haven't given any info about what this target is other than it's a RISC-V simulated using Verilator.

From: sajjad ahmed <sajjad.a...@gmail.com>
Sent: Wednesday 10 March 2021 06:38
To: RISC-V HW Dev <hw-...@groups.riscv.org>
Cc: tommy_...@hotmail.com <tommy_...@hotmail.com>; sajjad ahmed <sajjad.a...@gmail.com>
Subject: Re: [hw-dev] openOCD connection failing at examine statge
 

sajjad ahmed

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Mar 10, 2021, 1:40:27 PMMar 10
to RISC-V HW Dev, tommy_...@hotmail.com, sajjad ahmed
actually i am trying to configure debug module of pulp platform with ibex core. and facing this issue. i think the debugger can not halt the core but why is it so, i have checked the connections and haven't found any problem in that

Tommy Murphy

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Mar 10, 2021, 4:07:15 PMMar 10
to sajjad ahmed, RISC-V HW Dev
Do you mean this?


Perhaps that project's community might be able to advise since, as far as I can see, OpenOCD is doing the right thing to halt the target but it's just nott happening so maybe it's something in the target itself?

From: sajjad ahmed <sajjad.a...@gmail.com>
Sent: Wednesday 10 March 2021 18:40

To: RISC-V HW Dev <hw-...@groups.riscv.org>
Cc: tommy_...@hotmail.com <tommy_...@hotmail.com>; sajjad ahmed <sajjad.a...@gmail.com>
Subject: Re: [hw-dev] openOCD connection failing at examine statge
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