micro-architecture specifications (MAS)

[Simha]

Hello group,

what are the RISC-V ISA based processor core micro-architecture specifications (MAS), available as free & open ?

Thanks,

Simha. 

[Luke Kenneth Casson Leighton]

Hi Simha, technically speaking, none of them, in the usual sense of libre and open, because Trademark Law takes top precedence, for extremely sensible reasons.

As someone who holds a Certification Mark on documents and design files that are released under the GPLv3+ I understand the critical importance of Trademark Law very well, and the Foundation has this aspect absolutely right.

The actual specification documents for RISCV are open access. They are on the github repo and the riscv website, you can find them with a goigle search much easier than i can type on this damn phone.

It depends from that point on what you intend to do. Commercial ventures are treated differently from libre ones, and not mentioning the registered trademark RISCV at all... it's complicated basically.

The main thing you need to know is, it's not a freeforall, that would create total chaos and bring the entire ecosystem into disrepute, hence why Trademark Law takes priority over anything else... but you are at liberty to get the full specs.

L.

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[schuyler.eldridge]

Narrowly: the RISC-V specification is an ISA specification only. An implementer is free to make whatever microarchitectural decisions they want to implement the RISC-V ISA specification. Hence there exists no Microarchitecture Specification (or: the RISC-V specification has no business saying what branch predictor you should use or how many pipeline stages you have).

Many reference implementations do exist under various free and open licenses. Rocket and BOOM are two examples. Myriad others exist.

Note: an implementer may infringe microarchitecture patents while designing a microarchitecture (while the RISC-V ISA is intended to be patent unencumbered). This is the same risk that any company/individual in the CPU business faces, however.

[David Lanzendörfer]

Hi
As Luke already mentioned: The trade mark law takes precedence over copyright
or better it picks up there where copyright doesn't work anymore anyway.
That's what we're working on fixing right now with our new LibreSilicon public
license which I hope to present to you folks together with the first PearlRive
test wafer at a talk at the congress.

Simplistically spoken: The GPL just doesn't cover IP cores and ISAs and the
like, you could publish it as well public domain, because the GPL doesn't
protect you from someone just using it in their commercial chips without
disclosing their design or giving you a cent.

You can however protect the technology with which the IP core has been silicon
verified under trade mark law and protect the IP this way.
That's what we're working out right now in text.

The IP/trade mark for LibreSilicon will be held by our LibreSilicon foundation
in Berlin and will implicitly grant licenses to everyone.
If there is a big commercial company starting to use it however, might go
there and discuss whether they don't wanna pay something of their revenue to
the community as a sign of gratitude.

Cheers
David

[Lakshminarasimhan Raghunathan]

 Rocket and BOOM are implementations at RTL level and MAS are not published.

I am looking for plain Micro-architecture specifications for a RTL designer to start working on.

Thanks.

[schuyler.eldridge]

There's the argument of "good code is documentation." :)

 Also, note that Rocket and BOOM are also core generators, as opposed to plain RTL designs. This level often lets you reason about the microarchitecture better due to software abstractions. However, it makes it more difficult to have a fixed document describing a single microarchitecture in the space of what they cover.

While not full microarchitecture specifications, there are a number of documents related to the microarchitecture of BOOM and Rocket that you may find useful:

  - https://ccelio.github.io/riscv-boom-doc/

  - https://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-157.pdf

  - https://www.lowrisc.org/docs/tagged-memory-v0.1/rocket-chip/ (this is outdated, though)

Others may have documents for their specific implementations.