Assistance with Designing Full Address Calculator for High-Performance Branch Predictor on RISC-V Core

[Hiruna Vishwamith]

Dear RISC-V HW Group,

I am currently working on implementing a high-performance branch predictor for a RISC-V core on an FPGA. While studying the paper "Low-Cost, High-Performance Branch Predictors for Soft Processors", I came across the following statement:

"ASIC processor implementations use a BTB since the cache latency dominates the clock cycle, leaving no room for further action. This is not true in an FPGA implementation where memory is generally faster than logic. This creates an opportunity to precalculate the target address for branches and thus eliminate the BTB."

The paper introduces a component called the Full Address Calculator, which is used to precalculate branch target addresses in FPGA-based designs. I would greatly appreciate any instructions or guidance on how to design such a component, specifically optimized for a RISC-V core on an FPGA.

Any advice or references you can provide would be highly valuable.

Thank you.

Best regards,
Hiruna Vishwamith