Hypervisor support in RISCV

[John Session]

Hello

I am trying to implement Hypervisor support in the RISCV CPU that i am working on. The target application is real-time automotive.

So i understand that i need to add the H-extension CSR registers and CSR instructions.

Now Hypervisor support will require two level memory paging scheme to translate the Virtual address to Physical address.

So my questions are:

1. Is it possible to realise this two-level memory paging scheme with an MPU or the only solution is to realise an MMU. I am thinking about the MPU for more deterministic and faster operation for the target application.
2. M-mode will be implemented, by default. Do i also need to provide support for [S, U] mode.
3. RISC-V provides the M-mode PMP scheme to support memory protection. However, if a two level memory paging scheme is implemented (either via an MPU or MMU), does the core still need to support PMP?

Thanks in advance.

[Valentin Nechayev]

hi,

Sat, Nov 23, 2024 at 04:05:11, johnsessionjr wrote about "[hw-dev] Hypervisor support in RISCV":

> 1. Is it possible to realise this two-level memory paging scheme with an

> MPU or the only solution is to realise an MMU. I am thinking about the MPU
> for more deterministic and faster operation for the target application.

If this is hypervisor according to the spec, yep, MMU is required.
You canʼt implement it without address translation, i.e. when address
at memory bus differs from one from an ISA command.

You may implement something different but I canʼt imagine how you can
provide hosting for different guest systems at the same time without a
mechanism to disperse the same guest-visible address to different
physical locations.

(A program emulation is, well, possible, but will cost too much.)

> 2. M-mode will be implemented, by default. Do i also need to provide

> support for [S, U] mode.

Again, yes. Just by the letter of the law (specification).

> 3. RISC-V provides the M-mode PMP scheme to support memory protection.

> However, if a two level memory paging scheme is implemented (either via an
> MPU or MMU), does the core still need to support PMP?

If you want to protect something M-mode specific from the supervisor -
yes, it needs.

OTOH various different ways exist - for example, you may add a
separate security processor for which the main one is fully
subordinate. Iʼve seen such designs (in ARM world, but the method is
universal).


-netch-