Newbie, starting to Learn Rocket Core and RISC-V Recommendation

[Nattapon Donratanapat]

Hello, 

I have just started my PhD school last month and I have assign to learn everything about RISC-V and rocket core. I have spent about a month-ish so far into learning it and still have no idea where to start. I have learned some of the Chisel syntax and looking into the Scala source code in the rocket core repo. I still have no idea what is going on in the core and pretty lost at this point. I just need a suggestion as a way to start learning the system. 

Thank you,

Nattapon Donratanapat

[Sathya Narayanan N]

Hello,

My bit of suggestion, based on personal experience 

It is normal to have such a problem. Start with blogs, news articles and other magazines hwich talk about RISCV. Get an idea what is RISCV all about (from a layman's point of view). Then, you start with learning the RISCV - ISA. It is the core and from it all the things evolves.  Slowly, you will get used to the terminologies and a big picture might evolve in your mind. From there on, you can start focusing on smaller areas. Over a period of time, you will try to grasp everything related to RISCV. Dont try to rush up, things will fall in place over a period of time.

Note: Hope you are exposed to fundamentals of computer architecture and operating system.

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 regards,
Sathya  

 

[Paul Miranda]

If you already know Verilog or VHDL (and not Scala/Chisel) you would probably find it easier to follow the PULP project's RISCY or Ariane cores, which they put on github...

http://www.pulp-platform.org/

While I like the idea of a modern object-oriented way of building hardware, in practice it's not easy to follow what is going on.

[atthec...@gmail.com]

I would second looking at the Pulp stuff; it is well written. I would not recommend Rocket to determine how to build a RISC-V as it is a difficult starting point.

For a more C-like hardware version of RISC-V there are my designs on GitHub at https://github.com/atthecodeface/cdl_hardware.git (under cpu/riscv).

This is in CDL, which is a simple synthesizable C-syntax hardware description language, and so it is simple for C folks to comprehend.

These are also micro controller style pipelines (in-order, two-stage to five-stage pipelines, no floating point, etc).

--Gavin

[Jack Koenig]

If you do wish to learn how rocket-chip works, I suggest starting with a gentler introduction to Chisel https://github.com/ucb-bar/generator-bootcamp and perhaps Scala in general https://www.coursera.org/learn/progfun1

There are also simpler RISC-V pipelines also implemented in Chisel intended for educational purposes: https://github.com/librecores/riscv-sodor

Finally, if you have Chisel-specific questions you can ask on the chisel-users list https://groups.google.com/forum/#!forum/chisel-users or on StackOverflow https://stackoverflow.com/questions/tagged/chisel

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