[riscv-hw] RV128I instructions in RISC-V

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Hemendra Rawat

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Dec 10, 2015, 1:42:21 PM12/10/15

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Hi All,

I want to implement few custom instructions for one of my research
projects. My custom
instructions work on two 128 bit source registers and produce one 128
bit output. I also want to make some performance measurements as well
with the custom instructions.

I wanted to enquire if the Rocket core or the RISC-V simulator
supports implementation of 128 bit
custom instructions ? I would be great if someone can help me with this query.

Thanks

Hemendra Kumar Rawat
Graduate Student
Department of Electrical & Computer Engineering
Virginia Tech

Andrew Waterman

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Dec 10, 2015, 4:24:47 PM12/10/15

to Hemendra Rawat, hw-dev

Hi Hemendra,

Rocket is RV64-only and Spike is RV32- and RV64-only. Although it
wouldn't be too hard to adapt either, we haven't done so because of a
bigger problem: we don't have any way of generating code for it.
AFAIK, we'd be the first 128-bit GCC target, which is a row I do not
wish to hoe.

For your experiment, you could either hack Spike, or find another way
to get 128 bits in and out of the coprocessor. One hack that comes to
mind is to use even/odd register pairs, so each 5-bit register
specifier refers to two adjacent registers. To be clear, I think this
is a bad ISA design, but it might suffice for your purposes.