Processor Trace Group

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Gajinder Panesar

Apr 26, 2018, 10:11:00 AM4/26/18
to RISC-V HW Dev

We are creating a Processor Trace Group with the following charter:


    Processor Trace Group Charter

    Chair: Gajinder Panesar, UltraSoC, Co-Chair: Hugh Okeeffe, Ashling


The group shall standardize both a hardware interface to the RISCV core and a packet/data format which will enable the development of commercial and open source trace encoders to be supported by any tools vendors.

        The interfaces are to provide enough information for:

                a. Instruction Trace.

        The interfaces should be suitable for in-order and out-of-order cores with extensions.

        The group will standardize the data format for:

                a. Compressed branch trace so that program flow can be reconstructed by debugging tools.

  The group’s progress shall be evaluated after one year at which time the charter may be revised if necessary to narrow the scope of effort.


We have a number of parties who have expressed interest already. Please get in touch if you would like to be involved and we will try arrange an initial get together at the Barcelona workshop. We will schedule and start regular meetings soon.



Gajinder Panesar

May 10, 2018, 6:39:00 AM5/10/18
to RISC-V HW Dev

Dear all,


  The group, Processor Trace Task Group, has been set up. If you would like to join the group, you need to ask via Sue Leininger ( You will need to have a login.

  We are having a face-to-face in Barcelona today but will try and get things, such as meetings etc, set up shortly.





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