Hypervisor support in RISCV

[J O]

Hello

I am trying to implement Hypervisor support in the RISCV CPU that i am working on. The target application is real-time automotive.

So i understand that i need to add the H-extension CSR registers and CSR instructions.

Now Hypervisor support will require two level memory paging scheme to translate the Virtual address to Physical address.

So my questions are:

1. Is it possible to realise this two-level memory paging scheme with an MPU or the only solution is to realise an MMU. I am thinking about the MPU for more deterministic and faster operation for the target application.
2. M-mode will be implemented, by default. Do i also need to provide support for [S, U] mode.
3. RISC-V provides the M-mode PMP scheme to support memory protection. However, if a two level memory paging scheme is implemented (either via an MPU or MMU), does the core still need to support PMP?

Thanks in advance.

Best Regards

J.Osmany