Doubts regarding RAM interface and csrs required for RV32I

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Rathish A T

Jul 4, 2021, 8:28:21 AMJul 4
to RISC-V HW Dev

Hello , i am a undergrad student designing a risc v processor in verilog to get in grips with the architecture and fpga usage .
i have already written a  single cycle  design which executes at OP ,OPIMM, LUI, AUIPC, BR, JAL,JALR.

i have simulated using verilog test benches and observed that all instructions these instructions work as intended .
    • but i am very confused as to the use of FENCE , ECALL and EBREAK instructions and i am facing difficulty as to approaching the implementation of this instruction .And reading 2.7,2.8,2.9 sections are  making me further confused as to their working. So any resource for understanding this would be helpful
    • my second difficulty comes in ram access . currently i have designed a ram of width 8 and depth of 256 . hence for writing and reading 1 word 4 locations are read in 1 cycle . similarly 2 loc read for halfword and 1 for byte . this was done under the impression that addresses to store byte can be 1 byte aligned and adresses to store halfword is 2 byte aligned .though this works in simulation , this results in an unsynthesisable design . hence I am trying to redisgn the ram controller . can we assume that all addresses to memory are 4 byte aligned ?
    • 3rd is how to connect my core to the risc compliance tests . what inputs , csrs and system functions are needed to do it . any resouces or existing work in verilog will be appreciated 
Thank you
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