> Can anyone tell me what constitute an misaligned access in RISCV? It was
A misaligned access is any access (load or store) to an address that
meets the following criteria:
- for a 16-bit half-word, address bit 0 is set.
- for a 32-bit word, any of address bit 0 or address bit 1 is set.
- for a 64-bit double-word, any of address bits 0, 1, or 2 are set.
- for a 128-bit quad-word, any of address bits 0, 1, 2, or 3 are set.
> 1. For 32b accesses, for a single byte access, can the byte be located in
> any of the in four bytes in the data (or register)? If so, which RISCV
> instruction will generate such a load/store?
The question, as written, doesn't make sense: the former half of the
question specifies a 32-bit access, but the second half of the
question mentions a single byte access.
LB and SB will generate single-byte accesses. It's impossible to be
misaligned, since bytes are the smallest addressable unit.
LW and SW are instructions which transfers 32 bits at a time.
> 2. Same question for 2B accesses. Can the 2B be located anywhere in the 4B
> data (or register)?
No; an aligned half-word access is naturally aligned on half-word
boundaries (meaning, address bit 0 is always zero). They can be
generated with LH or SH instructions.
> 3. For implementations with caches, for misaligned accesses access across
> cacheline boundary (let's ignore the case of crossing TLB boundary for now),
> the HW needs to split the transaction into two, correct? This should go
> without saying, but I like to understand the intent of the architecture.
That is correct, yes.
Samuel A. Falvo II