Rocket: identifying source pin of external interrupt?

[Gabriel L. Somlo]

Hi,

I configured and built my RocketChip with "new WithNExtTopInterrupts(4)",
which as expected generated a 4-bit interrupt input signal to the
ExampleRocketSystem module: "input [3:0] interrupts,".

It is my understanding that all four of these count as "external", and
that if any of them is asserted, I'd get a trap, provided bit 3 (MIE)
of the "mstatus" CSR is enabled, *and* bit 11 (MEIE) of the "mie" CSR
is also enabled (dealing with machine mode only, for now).

If I'm right so far, how would I figure out which of the several
external interrupt pins was asserted once I get to the trap handler
and realize MEIP is asserted in "mip", and "mcause" says it's an
external interrupt (0x800000000000000b)?

Is there some PLIC specific CSR or register I could read to get that
information?

Thanks,
--Gabriel

[be...@nvidia.com]

Yes, more or less.  Privileged ISA Spec Chapter 7 is pretty helpful for understanding this:

The target sends an interrupt claim message to the PLIC core... On receiving a claim message, the PLIC core will atomically determine the ID of the highest-priority pending interrupt for the target and then clear down the corresponding source’s IP bit. The PLIC core will then return the ID to the target.

Rocket's PLIC implements this communication with memory-mapped registers.  See PLICConsts in devices/tilelink/Plic.scala for the exact mapping of the memory space within the PLIC.

-Ben

[ilamparithy vijayan]

Hi ,

I LIke to have same configuration, can you suggest me how intr works