RISC-V 'CI' aka running RISC-V in a browser/cloud

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Martin Strubel

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Nov 1, 2019, 6:36:46 AM11/1/19
to RISC-V HW Dev
Hi list,

I though I'd share some openSource approach to let a RISC-V spin in the cloud - a few 1000 times slower than reality, but still fast enough to run the ISA tests and - for fun - to talk to the SoC through a virtual UART.
Thanks to the docker community, this can all run in the browser without having to install a lot of software (let aside resolving dependencies).

The other good thing is that this integrates nicely into github so that when breaking stuff during development, this will show.
The actual engine behind it is the open source GHDL simulator (https://github.com/ghdl/ghdl/). So the entire thing is pretty VHDL specific, however with a bit of work this could also done with license-free verilog simulators - which would be nice to have some day, to do synthesis the 'opensource continuous integration' way as well (with yosys).

For those wanting to play with it, I dropped some instructions for quick start:

https://section5.ch/index.php/2019/10/24/risc-v-in-the-loop/

Cheers,

- Martin

why...@f-cpu.org

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Nov 1, 2019, 12:49:13 PM11/1/19
to Martin Strubel, RISC-V HW Dev
On 2019-11-01 11:36, Martin Strubel wrote:
> Hi list,

Hey Martin !

> For those wanting to play with it, I dropped some instructions for
> quick start:
>
> https://section5.ch/index.php/2019/10/24/risc-v-in-the-loop/

Great work !

It's so sad that so few people recognise the power of VHDL and GHDL...

> Cheers,
>
> - Martin
yg

Martin Strubel

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Feb 20, 2020, 7:52:57 AM2/20/20
to RISC-V HW Dev, sp...@section5.ch, why...@f-cpu.org

Hi there,

I thought I'd follow up on the GHDL side..
Thanks to Tristan Gingolds incredible work to support Synthesis with GHDL through yosys, these kind of SoCs now synthesize in the open cloud based on VHDL, like the Verilog crowd.
There are some issues to be resolved with RAMs, therefore my riscv32i approach 'pyrv32' does not yet play 100% nice, but synthesizes (with a few workarounds) so far that UART, JTAG and SPI are chatting on a ECP5 Lattice Versa devkit.

The development (ghdlsynth branch) is here: https://github.com/hackfin/MaSoCist/tree/ghdlsynth_release

Instructions on how to get it spinning using Docker (no SW installation dance):


Greetings,

- Martin

Sivan !

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Mar 8, 2021, 8:13:02 PMMar 8
to RISC-V HW Dev, sp...@section5.ch, why...@f-cpu.org
Strange, all the three links in this messsage point to an errro establishing a Data base connection page

risc V on the cloud.png.

Tommy Murphy

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Mar 9, 2021, 3:58:15 AMMar 9
to RISC-V HW Dev, Sivan !, sp...@section5.ch, why...@f-cpu.org
There are only two links in the previous email and they both work without error for me.

Your embedded graphic, on the other hand, doesn't appear.

From: Sivan ! <s9952...@gmail.com>
Sent: Tuesday, March 9, 2021 1:13:02 AM
To: RISC-V HW Dev <hw-...@groups.riscv.org>
Cc: sp...@section5.ch <sp...@section5.ch>; why...@f-cpu.org <why...@f-cpu.org>
Subject: Re: [hw-dev] RISC-V 'CI' aka running RISC-V in a browser/cloud
 
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Sivan !

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Mar 9, 2021, 6:02:12 AMMar 9
to Tommy Murphy, RISC-V HW Dev, sp...@section5.ch, why...@f-cpu.org
All three links work fine for me here now, I tried (now) it from the gmail window, and on the groups.google.com page, all three links work fine. There was a problem, I did say it is "strange" when I reported this error with screenshot, because it appeared to be an access problem very similar to the access problems I have experienced with certain sites, which are sites generally well functioning, including a certain forum sites, (about which I will ask in the concerned forum.)

Thank you for confirming, 
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