Understanding how to add VHDL peripherals to Rocket Chip

[alzubai...@gmail.com]

Hi everyone,

I am a computer science student in my last year I would like to work on SOC. I already did a project making a simple soft-core processor using FPGA and I would like to continue in that path, that's why Rocket chip got my attention.

My goal is to add several peripherals in VHDL to the rocket chip to make my own SOC based on rocket chip  (not based on SOCs like lowrisc & warpbird). But I am having hard time understanding how to connect peripherals (say UART for example) using the rocket chip generator.

In Yunsup Lee draft there is this figure:

I would like to understand several things:

1. The HOSTIO pins are not used and not generated in the Verilog code of the ExampleRocketSystem(I suppose its the instance name of Rochet Chip)  module because it's only used for emulation is that right ?
2. In the Verilog code of the ExampleRocketSystem, there are three type of ports the debug, mmio_axi4_0 and l2_frontend_bus_axi4. Since  l2_frontend_bus_axi4 are not used in figure above, I would like to know what is it used for ?
3. mmio_axi4_0 should it be treated as mmio or axi protocol ?

I have read the The Rocket Chip Generator draft which can be found here: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html

In this document there is a figure detailing the rocket chip (figure A) which is very similar to the one in Yunsup Lee's draft (figure B).

                                         Figure A                                                                                                                                                                     Figure B     

      4.  In figure A "TileLink/AXI4 Bridge" I cant draw a line between rocket chip and the outside world ? where are the HOSTIO & MMIO which are supposed to be the only output of the rocket chip ?  

      5.  I find this figure a lot simpler since, if I understood correctly, I only have to add the peripherals next to the "AHB & APB Peripherals" ?

      6.  Is there some kind of tutorial or documentation explaining how to connect the differents IO of the modules to the Rocket chip ?

      7.  Should give up the idea of adding modules in in VHDL/Verilog and learn Chisel (which I just started) ?

Sorry for asking a lot of questions but I have been stuck for 3 weeks now.

Thank you all.

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Apr 16, 2018 at 12:58 PM, <alzubai...@gmail.com> wrote:

> 6. Is there some kind of tutorial or documentation explaining how to connect the differents IO of the modules to the Rocket chip ?

i would very much like to know the answer to this as well. a simple
"Here is how to connect a simple AXI4 Verilog / VHDL peripheral
directly integrated into a RocketChip Project just run make" would be
extremely valuable.

> 7. Should give up the idea of adding modules in in VHDL/Verilog and learn Chisel (which I just started) ?

no - lots of people have VHDL and Verilog sources that have been
verified and silicon-proven: rewriting them all is totally
unrealistic: *somewhere* there will be someone who has had to add VHDL
/ Verilog peripherals.

l.

[David Lanzendörfer]

Would there be an interest into helping to crowdfund our LibreSilicon project?
We could use some additional finances ^^

Cheers
David

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Best regards

CEO, David Lanzendörfer
Lanceville Technology
22A, Block2, China Phoenix Mansion,
No.2008 Shennan Boulevard,
Futian District, Shenzhen

[david mlw]

I think the TileLink is the key to the questions, TileLink crossbar should be more configurable to hold Rocket Cores and other any master/slave ports.

Where are more examples of TileLink?

Liwei Ma.

在 2018年4月16日星期一 UTC+8下午7:58:27，alzubai...@gmail.com写道：