[riscv-hw] What is V-Scale

[Jimmy Situ]

Hi, All

I found there is an info about RISC-V update durning the 3th workshop, 

V-Scale: Verilog implementation of Z-Scale, opensourced Sep 2015

Could someone tell me more information about this V-Scale and Z-Scale, I google it and seems found nothing.

[Samuel Falvo II]

Z-Scale is a microcontroller implementation of the RISC-V 32-bit
instruction set. It is written in Chisel, a higher-level hardware
description language.

V-Scale is the Verilog output produced from Chisel after processing
the Z-Scale source code. It's a separate project because not everyone
is capable of running Chisel.

--
Samuel A. Falvo II

[Alex Bradbury]

Z-Scale is a microcontroller-class implementation of the RISC-V ISA in
Chisel. More info in Yunsup's slides from the 2nd RISC-V workshop
http://riscv.org/workshop-jun2015/riscv-zscale-workshop-june2015.pdf

V-Scale is a Verilog implementation of this design
https://github.com/ucb-bar/vscale

Best,

Alex

[Krste Asanovic]

V-scale was manually rewritten in the hope of being readable.

(whether any human-readable Verilog exists is open to debate)

Krste

[Samuel Falvo II]

On Mon, Jan 11, 2016 at 2:07 PM, Krste Asanovic <kr...@berkeley.edu> wrote:
> V-scale was manually rewritten in the hope of being readable.

Ahh, I wasn't aware of this. Thanks!

[Albert Forte Magyar]

V-scale implements the same pipeline as Z-scale with minor micro architectural differences. The two are pin-compatible and connect to AHB interfaces for compatibility with FPGA bus and memory IP.

[Joel Vandergriendt]

Out of curiosity, does anyone have numbers comparing size/Fmax for zscale vs vscale?

[蔡宗裕]

Dear Albert,

Have you put this v-scale verilog code onto FPGA to run verification?

If yes, do you have the .xpr project file?

Best regards,

Johnny

Jimmy Situ於 2016年1月12日星期二 UTC+8上午12時14分21秒寫道：