memory space mapping for lowRiscv

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Claire M. M. Wong

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Jul 11, 2018, 8:41:19 PM7/11/18
to RISC-V HW Dev
Hi all,

I noticed there is a significant change in memory space mapping between lowriscv project v0.2 (developed for KC705) and project v0.3 onwards (developed for NexyDDR). Is the memory mapping has to be done in such way subject to the hardware board?

In other words, suppose that I am trying to port project v0.5 to KC705, should I also change the memory space allocated for the IO and Mem?

What about the drivers for the baremetal examples? are they subjected to the project's version and independent of the board? again if I would like to run the bare metal example Hello World for v0.5 implemented on KC705, should I be using the drivers that come with v0.5 or I have to use the ones provided in v0.2? 

Sorry if I sound very silly as I am still trying to figure out how to get things work with lowriscv project :) 
My main aim is to implement v0.5 on KC705. After several changes have been done, the work is still not successful. Therefore, I am trying to troubleshoot as much as I could to figure out what I might have missed.

And I really need your advice and opinions. They will be very much appreciated :D

Regards
Claire

Dr Jonathan Kimmitt

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Jul 12, 2018, 7:49:00 AM7/12/18
to Claire M. M. Wong, RISC-V HW Dev

Dear Claire,

From your description it is impossible to know what is wrong with your 'several changes'.

The main memory space by necessity will be larger on KC705. Other than that the memory map will be specific to the release and not to the board.

The only files which should definitely be taken for the KC705 from previous releases are the Xilinx pinout and the dynamic memory config.

Did you begin your port by copying the v0.5 nexys4ddr directory to kc705?

Did you adapt the Ethernet module design to use MII instead of RMII ?

Did you avoid mixing drivers, memory maps or RISCV files from different releases to prevent incompatible API changes from being propagated ?

Did you remove the peripherals that are Nexys4DDR only (everything except serial, Ethernet, and SD-Card)

Did you simulate the reworked parts of the design in Verilog ?

If you are still stuck you need to provide more details of the changes you tried to make.

Regards,
Jonathan
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Robert Mullins

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Jul 12, 2018, 7:58:45 AM7/12/18
to Dr Jonathan Kimmitt, Claire M. M. Wong, RISC-V HW Dev
Hi Claire,

Nice to hear you are experimenting with lowRISC. I hope Jonathan is
able to help.

The lowrisc-dev mailing list might be best for this sort of discussion:
https://listmaster.pepperfish.net/cgi-bin/mailman/listinfo/lowrisc-dev-lists.lowrisc.org

Let us know how we can help by providing a few more details.

v. best,
- Rob.
> https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/d57bca23-dd81-9278-bb42-b31625c2af75%40cam.ac.uk.

Claire M. M. Wong

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Jul 12, 2018, 10:31:26 AM7/12/18
to Robert Mullins, Dr Jonathan Kimmitt, RISC-V HW Dev
Thanks for the heads-up.

As for Jonathan queations:

Yes I started the porting by copying the v0.5 nexys4ddr directory to kc705.

I commented the ethernet part in release v0.5. I want to minimise the scope of troubleshooting. I will deal with this part later on. 

As for the drivers, yes I did mix and modify a little from other releases. But not for the memory maps. 

Yes the NexyDDR only peripheral has been removed, that also includes the ADD_HID

I have run the fpga simulation. I directly try out the make hello and it didnt work. As in I didnt get the Hello Work printout on the terminal.

Just to be sure, is the drivers are strictly specific for each release?




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