implementation of lb,sb--lh,sh

[Zeeshan Rafique]

Hello everyone,

I am a little bit confused while implementing lb,lh, and sb, sh instructions. 

My question is that on the execution of these instructions they (lb, lh) will fetch the most lower byte ([7:0], [15:0]) of a word or it can fetch any byte from word according to the given address.

If it can fetch any byte then should we design our memory byte, half word, or word align.

Your time will be appreciated.

Thanks  

[Rishi Khan]

The RISC-V spec says that it is up to the implementor whether to throw an unaligned hardware exception or not. Many implementations simply fetch the entire double-word, and then return the correct size (i.e. byte, half-word, word, double-word). Therefore, an unaligned load would throw an exception. It’s up to you.

--
You received this message because you are subscribed to the Google Groups "RISC-V HW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+un...@groups.riscv.org.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/646778b9-8a85-4f0c-80bc-fe5626bd128fn%40groups.riscv.org.

[Zeeshan Rafique]

okay... The instructions are generated from the GCC and their addresses so. If we throw an unaligned hardware exception don't you think we loose that instruction.

OR we will handle that exception by setting (align) those addresses each time on exception call?

[Nick Knight]

Hi Zeeshan,

I don't think I understand your question.

The RISC-V memory system is byte-addressable, meaning that each memory address refers to a particular byte in memory. The lb/sb instructions load/store the byte at the given address, thus misalignment is impossible. The lh/sh instructions load/store the halfword whose two bytes reside at the given ("base") address and the subsequent address ("base plus one"); if the base address is odd, the access is considered misaligned and the behavior is implementation defined. Portable software should only issue aligned lh/sh instructions, those with even (base) addresses.

Best,

Nick Knight

--

[Zeeshan Rafique]

Hello Nick,

I am considering the I have a memory that is word-aligned (32-bits wide).

Is it necessary to implement the memory 1 byte wide? I don't think so. It's up to the designer how he designs the memory, it can be either 1 byte, 2 bytes, or 1 word(32 bits/4 bytes) wide.

Yes, the RISC-V memory system is byte-addressable, it means you can access any byte from the word, but the problem is that if you are working with word-aligned memory than the memory will perform only word-aligned operations like lw/sw. 

Now what I am doing is that (in case of sb instruction) I am fetching the word in which the amendment is required, then I apply changes to that particular byte of that word and then write it back to the location from it was fetched, so the other bytes will get not disturb in this case.

Here is my RTL, please do let me know if I am doing any blunder.

 ////////////////sb///////////////////

always @(posedge clk) begin
    memory_in = memory[address];
     if (byte_enable == 3'b011)
          memory_in[31:24] <= storing_byte;
else if (byte_enable == 3'b010)
          memory_in[23:16] <= storing_byte;
else if (byte_enable == 3'b001)
          memory_in[15:8] <= storing_byte;
else if (byte_enable == 3'b000)
          memory_in[7:0] <= storing_byte;
end

//////////////////storing back/////////////

  always @(posedge clk) begin
    memory[address] = memory_in;  

end

"memory_in" is a register that stores the word after fetching and it will write back into memory in the next cycle at the location ("address"). whereas "storing_byte" is the input to the memory or the byte to be stored, and the "byte_enable" is used to tell that which byte is going to be amended.

Note: This scenario is tested and working properly but the purpose of posting a question is to clarify my skills and to know better solutions if there is any.

Thanks

[Shivam Potdar]

Hello Zeeshan, 

I certainly believe there would be people with higher level of expertise who would explain this better. 

But as far as I have seen, the practice is to have a 4 bit mask signal to enable particular bytes inside the word. The memory is laid out as 32 by X, and say if you want to perform SH, you would set the mask to 0011 or 1100.

You might like to look at the PicoRV32 external memory interface. This idea is explained quite well there. 

(https://github.com/cliffordwolf/picorv32#picorv32-native-memory-interface) 

I hope this helps. 

Regards 

Shivam Mahesh Potdar
4th (Senior) Year BTech (Electrical and Electronics Engineering)
National Institute of Technology Karnataka, Surathkal, India
mobile:  +91-9511893050
website:  shivampotdar.me
LinkedIn: shivampotdar99
email:  shivamp...@gmail.com | shivam....@nitk.edu.in

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/CAHnVyTP6nWCECpmDbm9JyJkFsu5mhSU7xc%3DgGRu2Z6PY9Qjhig%40mail.gmail.com.

[Zeeshan Rafique]

Ok thanks Shivam.

[Sober Liu]

Riscv-gcc generate naturally aligned address for load/store instructions (#define STRICT_ALIGNMENT 1).

And sure lb should be able to load each byte of the word, depends on the offset.

 

From: Zeeshan Rafique <zeeshanr...@gmail.com>
Sent: 2020年8月23日 16:13
To: Shivam Potdar <shivamp...@gmail.com>
Cc: Nick Knight <nick....@sifive.com>; RISC-V HW Dev <hw-...@groups.riscv.org>
Subject: Re: [hw-dev] implementation of lb,sb--lh,sh

 

External email: Use caution opening links or attachments

 

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/CAHnVyTNTRSQf3eXa806CUWOSQd-EcQBusfQK0bN2ymw8C%3DHVVQ%40mail.gmail.com.

[Hadir Khan]

Hello Zeeshan,

You can resolve this issue with the tilelink bus protocol or any other bus protocols in general. Generally it doesn't matter if your memory is byte aligned or word aligned. The controlling is done through masking. So say you want a full word read on address 0x0. You'll set the a_address = 0x0 and the a_mask = 1111. Each bit in a_mask represents active byte lanes. This will tell the device to read all 4 bytes. If you want to read a byte again you'll set a_address = 0x0 but this time your a_mask = 0001 this indicates to read from the first byte lane little endian aligned. So this problem is generally not related to an ISA but is specific to the implementation. All bus protocols enables you with such features. 

Regards,

Hadir

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/DM5PR12MB14971736F9731D789A9780DEAD590%40DM5PR12MB1497.namprd12.prod.outlook.com.