Tile Link address bus width on sbus in rocket-chip

Muhammad Ali Akhtar

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Mar 8, 2019, 7:06:27 AM3/8/19

to RISC-V HW Dev

Hello All,

Following project-template, I am trying to connect my custom peripheral to rocket-chip. The peripheral will do the dma to memroy to read and write data.

I have created the TLClient node and connected it to sbus for dma. My problem is that the memory address coming from peripheral is 42-bit wide, whereas the Tile Link edge object created for dma node provides 32-bit wide address.

Any idea how to set the address widget when creating a Tile Link Client node for sbus connection?

Muhammad Ali Akhtar
Principal Design Engineer
http://www.linkedin.com/in/muhammadakhtar

Henry Cook

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Mar 8, 2019, 5:01:39 PM3/8/19

to Muhammad Ali Akhtar, RISC-V HW Dev

Address widths are automatically calculated by diplomacy based on the devices visible from the point at which the client is attached to the bus. Put another way, the address width is a parameter that flows from managers to clients, and the only way to control the address width of a client is to control which addresses its node can see. If you are not seeing an expected address width at a client, I would check your bus topology graphml to ensure the client can actually see the large peripheral, and whether the peripheral's address range is actually as large as you expect it to be.

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/Henry

Muhammad Ali Akhtar

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Mar 12, 2019, 2:41:00 PM3/12/19

to Henry Cook, RISC-V HW Dev

Dear Henry,

Thanks a lot for your response. I used the diagrammer repo to get the graphml of my design (firechip) but the resulting graphml is very detailed with individual wires for each signal and its very hard to count the number of wires to get the address bits.

Any idea how to generate the simple graphml as shown in Figure-1 of carrv-2017 paper on tilelink?

Muhammad Ali Akhtar
Principal Design Engineer
http://www.linkedin.com/in/muhammadakhtar

Henry Cook

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Mar 12, 2019, 3:19:31 PM3/12/19

to Muhammad Ali Akhtar, RISC-V HW Dev

The scala generator dumps out a graphml file, I believe in the firrtl sub-directory. I usually use the free tool yed (https://www.yworks.com/products/yed) to view the resulting file and manipulate the layout.

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/Henry

Jerry Ho

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Oct 23, 2020, 5:13:36 AM10/23/20

to RISC-V HW Dev, he...@sifive.com

hey, recently I watched a youtube video in the chisel group, https://www.youtube.com/watch?v=Eko86PGEoDY I wonder if I can get the copy of your slides. Thank you so much! I found the Rocket chip generator's source code challenging to understand. Hope you can give me some suggections on how to dive into the details more easly.

Henry Cook

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Oct 23, 2020, 2:03:30 PM10/23/20

to Jerry Ho, RISC-V HW Dev

Thank you for your interest. You can view the slides here.

Chapters 1.3, 3 and 9 of the Chipyard documentation are all very useful in understanding how to use the rocket-chip codebase, and to some degree how it works internally. (rocket-chip is a library used by Chipyard.)