How to implement TLB refresh in RISCV so that any load access will trigger TLB MISS?

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Bill mike

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Jun 15, 2021, 4:45:51 AMJun 15
to RISC-V HW Dev
Hello, how to implement TLB refresh in RISCV so that any load access will trigger TLB MISS? The RISCV manual says that sfence.vma instruction seems to refresh TLB, but I did not see any TLB miss after executing this instruction. Is there any way to make any TLB miss happen
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