PULPino: FREE and OPEN-SOURCE RISC-V microprocessor system

718 views
Skip to first unread message

Andreas Traber

unread,
Feb 29, 2016, 4:30:44 AM2/29/16
to hw-...@groups.riscv.org
We are happy to share our FREE microprocessor system PULPino!
You can download the entire source code, test programs, programming
environment and even the bitstream for the popular ZEDboard, completely
for free under the Solderpad license.

What you will get is a competitive, state-of-the-art 32-bit processor
based on the RISC-V architecture, with a rich set of
peripherals, and full debug support. At ETH Zurich and Universita' di
Bologna
we have put many of the ideas that we have developed on our research on
ultra-low-power parallel processing (PULP project) into PULPino.
It is the little hip brother to its more serious bigger brothers.

Are you excited about it? Stop reading right now, and go to:
https://github.com/pulp-platform/pulpino
to download pulpino.

If you are not convinced easily, let us tell you more about the
details:

The core: PULPino is an open-source microcontroller system, based on an
optimized 32-bit RISC-V core developed at ETH Zurich and Universita' di
Bologna. The core has an IPC close to 1, full support for the base
integer
instruction set (RV32I), compressed instructions (RV32C) and partial
support
for the multiplication instruction set extension (RV32M). It implements
several
ISA extensions such as: hardware loops, post-incrementing load and
store
instructions, ALU and MAC operations, which increase the efficiency of
the
core in low-power signal processing applications.

Peripherals: For communication with the outside world, PULPino contains
a broad set of peripherals, including I2S, I2C, SPI and UART. The
platform internal devices can be accessed from outside via JTAG and SPI
which allows pre-loading RAMs with executable code. In standalone mode,
the platform boots from an internal boot ROM and loads its program from
an external SPI flash.

More features: To allow embedded operating systems such as FreeRTOS to
run, a subset of the privileged specification is supported. When the
core is idle, the platform can be put into a low power mode, where only
a simple event unit is active and everything else is clock-gated and
consumes minimal power (leakage). A specialized event unit wakes up the
core in case an event/interrupt arrives.

Not a toy design: PULPino is a mature design: it has been taped-out as
an ASIC in UMC 65nm in January 2016. The PULPino platform is available
for RTL simulation as well for FPGA mapping. It has full debug support
on all targets. In addition we support extended profiling with source
code annotated execution times through KCacheGrind in RTL simulations.

And it is free, no registration, no strings attached, you can use it,
change it, adapt it, add to your own chip, use it for classes,
research,
projects, products... We just ask you to acknowledge the source, and
if possible, let us know what you like and what you like and don't
like.

Open hardware, the way it should be!

The PULPino source code is available on github, see
https://github.com/pulp-platform/pulpino
For more information on PULPino and PULP see our websites:
http://pulp-platform.org, http://pulp.ethz.ch and
http://www-micrel.deis.unibo.it/pulp-project/

蔡宗裕

unread,
Mar 24, 2016, 6:16:49 AM3/24/16
to RISC-V HW Dev, atr...@iis.ee.ethz.ch
Dear Andreas,

I am Johnny from Taiwan.
I've successfully ported your Pulpemu FPGA platform onto my Zybo FPGA board.
Now I can SPI download the codes to the instruction memory location 0x00000000 and read back check correctly.
But after I set the boot address to 0x00000000 and start the device by set the fetch_en high,
it seem code is not running, nothing output on the gpio_out.
My sample code complied and dis-assembled as below, could you help me check what could be the problem?
Thank a lot in advance!

0000000000000000 <main>:
   0: ff010113           addi sp,sp,-16
   4: 00113423           sd ra,8(sp)
   8: 00813023           sd s0,0(sp)
   c: 01010413           addi s0,sp,16
  10: 1a1077b7           lui a5,0x1a107
  14: 00010737           lui a4,0x10
  18: f007071b           addiw a4,a4,-256
  1c: 00e7a023           sw a4,0(a5) # 1a107000 <main+0x1a107000>
  20: 1a1017b7           lui a5,0x1a101
  24: 00010737           lui a4,0x10
  28: f007071b           addiw a4,a4,-256
  2c: 00e7a023           sw a4,0(a5) # 1a101000 <main+0x1a101000>
  30: 1a1017b7           lui a5,0x1a101
  34: 00878793           addi a5,a5,8 # 1a101008 <main+0x1a101008>
  38: 00006737           lui a4,0x6
  3c: a007071b           addiw a4,a4,-1536
  40: 00e7a023           sw a4,0(a5)
  44: 00000297           auipc t0,0x0
  48: 000280e7           jalr t0
  4c: 00000793           li a5,0
  50: 00078513           mv a0,a5
  54: 00813083           ld ra,8(sp)
  58: 00013403           ld s0,0(sp)
  5c: 01010113           addi sp,sp,16
  60: 00008067           ret


Richard Herveille

unread,
Mar 25, 2016, 1:24:13 AM3/25/16
to 蔡宗裕, RISC-V HW Dev, atr...@iis.ee.ethz.ch
This answer might be completely wrong, but normally the RISC-V does not start execution from address 0. Probably that should be 0x200

Richard


Sent from my iPad
--
You received this message because you are subscribed to the Google Groups "RISC-V HW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+un...@groups.riscv.org.
To post to this group, send email to hw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/e2503d02-00b5-4566-b3a0-0c76a1b474ec%40groups.riscv.org.

Andreas Traber

unread,
Mar 25, 2016, 7:50:01 AM3/25/16
to 蔡宗裕, Richard Herveille, RISC-V HW Dev
Hi Johnny

Richard has a good point, although when you set the boot address on the
PULPino platform it actually only sets the upper 24 bits, the rest is
hard-coded into the CPU. The rationale behind it is that the boot
address also serves as the base address of the interrupt vector table in
our system which was a requirement we had for our many-core system so
that not all cores have to have exactly the same IVT.

Is this the whole objdump output or did you extract only main? As
Richard was already saying, the core will not start executing at 0, but
at another address, in our case 0x80. Similarly it needs to setup the
internal registers first before it can execute real code, e.g. setup the
stack pointer and so on. So if the snippet you sent us is all there is,
then all of this s missing.

It also looks like you are using the 64-bit version of the compiler,
e.g. the sd, addiw and ld instructions are used. Those are 64-bit only
instructions and not supported on our 32-bit core.

Cheers
Andy
>> https://groups.google.com/a/groups.riscv.org/group/hw-dev/ [1].
>> [2].
>
>
> Links:
> ------
> [1] https://groups.google.com/a/groups.riscv.org/group/hw-dev/
> [2]
>
> https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/e2503d02-00b5-4566-b3a0-0c76a1b474ec%40groups.riscv.org?utm_medium=email&amp;utm_source=footer

蔡宗裕

unread,
Mar 25, 2016, 8:39:51 AM3/25/16
to RISC-V HW Dev
Hi Andy,

I did change to use 32-bit compiler and load the program to 0x80 as you instructed. Now RISCV core can execute loaded code and light up LEDs as expected.
Thank Richard and your excellent answer to help me.

Best regards,
Johnny

蔡宗裕

unread,
Mar 30, 2016, 6:06:34 AM3/30/16
to RISC-V HW Dev
Dear Andy,

Sorry to bother you again,
After I further tested some codes as below,
the core seems run away after executed "j 17c <.L2+0xb4>" at address 0xb4.
Did I miss any internal register setting or set the 'wrong' compiler option?

led_flash.o: file format elf32-littleriscv


Disassembly of section .text:

00000000 <main-0x80>:
...

00000080 <main>:
80: fe010113 addi sp,sp,-32
84: 00812e23 sw s0,28(sp)
88: 02010413 addi s0,sp,32
8c: 1a1017b7 lui a5,0x1a101
90: 00010737 lui a4,0x10
94: f0070713 addi a4,a4,-256 # ff00 <.L2+0xfe38>
98: 00e7a023 sw a4,0(a5) # 1a101000 <.L2+0x1a100f38>
9c: 1a1017b7 lui a5,0x1a101
a0: 00878793 addi a5,a5,8 # 1a101008 <.L2+0x1a100f40>
a4: 0000a737 lui a4,0xa
a8: 50070713 addi a4,a4,1280 # a500 <.L2+0xa438>
ac: 00e7a023 sw a4,0(a5)
b0: fe042623 sw zero,-20(s0)
b4: 0c80006f j 17c <.L2+0xb4>

000000b8 <.L3>:
b8: 00000013 nop
bc: fec42783 lw a5,-20(s0)
c0: 00178793 addi a5,a5,1
c4: fef42623 sw a5,-20(s0)

000000c8 <.L2>:
c8: fec42703 lw a4,-20(s0)
cc: 06300793 li a5,99
d0: 0ae7dc63 ble a4,a5,188 <.L2+0xc0>
d4: 1a1017b7 lui a5,0x1a101
d8: 00878793 addi a5,a5,8 # 1a101008 <.L2+0x1a100f40>
dc: 00006737 lui a4,0x6
e0: a0070713 addi a4,a4,-1536 # 5a00 <.L2+0x5938>
e4: 00e7a023 sw a4,0(a5)
e8: 00000793 li a5,0
ec: 00078513 mv a0,a5
f0: 01c12403 lw s0,28(sp)
f4: 02010113 addi sp,sp,32
f8: 00008067 ret

Andreas Traber

unread,
Mar 31, 2016, 3:25:05 AM3/31/16
to 蔡宗裕, RISC-V HW Dev
Hi Johnny

It still looks like you are missing a crt0 that sets up the registers
first and takes care of zeroing BSS and so on.
The first instruction that is executed in the code you sent, is a stack
pointer manipulation (addi sp,sp,-32), but the core does not yet have a
valid stack pointer.

Take a look at the crt0 that is part of pulpino (sw/ref/crt0.riscv.S).
Either you can use this one directly or modify it to your needs, but you
really need to do register setup before you jump to main.

Cheers
Andy

J Osmany

unread,
Apr 18, 2016, 7:40:19 AM4/18/16
to Andreas Traber, hw-...@groups.riscv.org
Hello

Trying to install Pulpino, but getting problems:

1) ./update-ips.py
File "./update-ips.py", line 22
with open("ips_list.txt", "rb") as f:
^
SyntaxError: invalid syntax


2) python27 update-ips.py
Using remote git server g...@iis-git.ee.ethz.ch:pulp-project

Cloning into 'ips/apb/apb_gpio'...
g...@iis-git.ee.ethz.ch's password:


So what password should i use?


Best Regards

J.Osmany

________________________________________
From: Andreas Traber <atr...@iis.ee.ethz.ch>
Sent: 29 February 2016 09:30
To: hw-...@groups.riscv.org
Subject: [hw-dev] PULPino: FREE and OPEN-SOURCE RISC-V microprocessor system
--
You received this message because you are subscribed to the Google Groups "RISC-V HW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+un...@groups.riscv.org.
To post to this group, send email to hw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/1db772225ebf8ef568433a8c9195621d%40iis.ee.ethz.ch.

Andreas Traber

unread,
Apr 18, 2016, 7:58:51 AM4/18/16
to J Osmany, hw-...@groups.riscv.org
Hi

1) Looks like a problem with your python environment

2) Might come as a result from 1), I guess.
The remote you are seeing is our internal GitLab server where we
don't allow public access. The update-ips script is trying to guess your
remote that you used to download PULPino originally, i.e. from Github.
It seems that for some reason this has failed and it fell back to our
internal server. I cannot reproduce the issue locally, so it is
difficult for me to fix.

You can try and set the git remote explicitly by changing lines 56
to 62 in the update-ips.py script like so:

server = "https://github.com"
group = "pulp-platform"
remote = "%s/%s" % (server, group)

Please make sure you remove the if statement before this block.

Cheers
Andy

J Osmany

unread,
Apr 18, 2016, 12:12:00 PM4/18/16
to Andreas Traber, hw-...@groups.riscv.org
Hi

I think i have managed to get Pulpino installed okay.

I had to make a few changes to update-ips.py (as you had suggested, plus had to chnage the last line in the file). Updated version of update-ips.py thatg i used is attached.

Also attached in the log from the installation.



Best Regards

J.Osmany

________________________________________
From: Andreas Traber <atr...@iis.ee.ethz.ch>
Sent: 18 April 2016 12:58
To: J Osmany; hw-...@groups.riscv.org
Subject: Re: [hw-dev] PULPino: FREE and OPEN-SOURCE RISC-V microprocessor system
pulpino_update.log
update-ips.py
Reply all
Reply to author
Forward
0 new messages