Using iVarilog vs. VCS

[Nhon]

Hi, all,

Has anyone tried using iverilog instead of VCS for vsim? Simulation quality wise, is iverilog good enough for actual ASIC chip? Any idea how fast or slow iverilog is vs. VCS?

I vaguely remember some project (lowrisc?) has used this, but not sure. If so, can someone share the Makefile? I am interested in learning how the various simulation options are replaced by iverilog's.

If there is a better open source verilog, please let me know as well.

Thanks!

Nhon

[Palmer Dabbelt]

I tried earlier this week, but it looks like iverilog doesn't have support for SystemVerilog DPI, which the Rocket Chip test harness is written in.  Here's a vague bug report

  https://github.com/steveicarus/iverilog/issues/100

which convinced me to stop trying to make it work.  Rocket Chip supports Verilator out of the box, use the emulator directory.  Here's the Makefile

  https://github.com/ucb-bar/rocket-chip/blob/master/emulator/Makefile

I've had good luck with Verilator for RTL simulation.

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[Nhon]

Palmer,

Did you mean you have better luck using Verilator for TinyConfig or for the default config?

Thanks,

Nhon

On Saturday, October 1, 2016 at 10:30:51 AM UTC-7, palmer.dabbelt wrote:

I tried earlier this week, but it looks like iverilog doesn't have support for SystemVerilog DPI, which the Rocket Chip test harness is written in.  Here's a vague bug report

  https://github.com/steveicarus/iverilog/issues/100

which convinced me to stop trying to make it work.  Rocket Chip supports Verilator out of the box, use the emulator directory.  Here's the Makefile

  https://github.com/ucb-bar/rocket-chip/blob/master/emulator/Makefile

I've had good luck with Verilator for RTL simulation.

On Sat, Oct 1, 2016 at 9:54 AM, Nhon <nhon....@abeesemi.net> wrote:

Hi, all,

Has anyone tried using iverilog instead of VCS for vsim? Simulation quality wise, is iverilog good enough for actual ASIC chip? Any idea how fast or slow iverilog is vs. VCS?

I vaguely remember some project (lowrisc?) has used this, but not sure. If so, can someone share the Makefile? I am interested in learning how the various simulation options are replaced by iverilog's.

If there is a better open source verilog, please let me know as well.

Thanks!

Nhon

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[Palmer Dabbelt]

As far as I know, all Rocket Chip configs should work in Verilator. We
actually use Verilator for CI builds of Rocket Chip on Travis, since we can't
run propritary tools there:

https://travis-ci.org/ucb-bar/rocket-chip

Unless this has changed, all Rocket Chip commits need to pass all the tests on
Travis (using Verilator as a simulator) before they can be merged to master.
You can see the exact set of configs here:

https://github.com/ucb-bar/rocket-chip/blob/master/regression/Makefile#L43

DefaultConfig and TinyConfig are both on that list, so they're both regularly
tested on Verilator.

On Fri, 07 Oct 2016 09:50:35 PDT (-0700), nhon....@abeesemi.net wrote:
> Palmer,
>
> Did you mean you have better luck using Verilator for TinyConfig or for the
> default config?
>
> Thanks,
>
> Nhon
>
> On Saturday, October 1, 2016 at 10:30:51 AM UTC-7, palmer.dabbelt wrote:
>>
>> I tried earlier this week, but it looks like iverilog doesn't have support
>> for SystemVerilog DPI, which the Rocket Chip test harness is written in.
>> Here's a vague bug report
>>
>> https://github.com/steveicarus/iverilog/issues/100
>>
>> which convinced me to stop trying to make it work. Rocket Chip supports
>> Verilator out of the box, use the emulator directory. Here's the Makefile
>>
>> https://github.com/ucb-bar/rocket-chip/blob/master/emulator/Makefile
>>
>> I've had good luck with Verilator for RTL simulation.
>>

>> On Sat, Oct 1, 2016 at 9:54 AM, Nhon <nhon....@abeesemi.net <javascript:>>

>> wrote:
>>
>>> Hi, all,
>>>
>>> Has anyone tried using iverilog instead of VCS for vsim? Simulation
>>> quality wise, is iverilog good enough for actual ASIC chip? Any idea how
>>> fast or slow iverilog is vs. VCS?
>>>
>>> I vaguely remember some project (lowrisc?) has used this, but not sure.
>>> If so, can someone share the Makefile? I am interested in learning how the
>>> various simulation options are replaced by iverilog's.
>>>
>>> If there is a better open source verilog, please let me know as well.
>>>
>>> Thanks!
>>>
>>> Nhon
>>>
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>>> Visit this group at
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>>> .
>>>
>>
>>