Information on Debug Module Status Register Bits

[Gattu Vinay]

Hello, folks! 

Debug Module Status(0x11) register let us know about the status of the harts. Could someone please let me know if 'allhalted' and 'allrunning' are complementary i.e., if allhalted = 0 then allrunning = 1 and vice versa.

Thanks,

Vinay

[Liviu Ionescu]

> On 20 Nov 2018, at 11:37, Gattu Vinay <vinay...@gmail.com> wrote:
>
> Hello, folks!
>
> Debug Module Status(0x11) register let us know about the status of the harts. Could someone please let me know if 'allhalted' and 'allrunning' are complementary i.e., if allhalted = 0 then allrunning = 1 and vice versa.

in a multi-hart device probably not, what if one hart is halted and all the other are running?


regards,

Liviu

[Tommy Murphy]

On Tuesday, 20 November 2018 09:37:51 UTC, Gattu Vinay wrote:

Hello, folks! 

 i.e., if allhalted = 0 then allrunning = 1 and vice versa.

No - allhalted and allrunning will be 0 if some but not all selected harts are running.

https://github.com/riscv/riscv-debug-spec/blob/master/riscv-debug-draft.pdf

 

allrunning This field is 1 when all currently selected harts are running
allhalted This field is 1 when all currently selected harts are halted.

My reading of this is:

allrunning == allhalted == 0 if some but not all selected harts are running

if allrunning == 1 then allhalted must be 0

If allhalted == 1 then allhalted must be 0

allrunning == allhalted == 1 is illegal

[Tommy Murphy]

Maybe simpler as a truth table:

 allrunning  allhalted  Description
 0           0          some but not all selected harts running
 0           1          all selected harts halted so allrunning is implicitly false
 1           0          all selected harts running to allhalted is implicitly false
 1           1          illegal state