Abstract command to access memory

[won ho yoo]

Hi, I am trying to simulate the RISC-V rocket-chip with my environment based on Verilog.

What I'm trying to do is giving the abstract command for accessing the memory (which stays outside from the rocket chip) by JTAG interface.

What I understand by the RISC-V Debug Specification is that the RISC-V will access the memory based on abstract command from the Core.

So what it should be is read/ write the memory by Core interface.

What I am confusing is that is there any need of another access point to memory for RISC-V when accessing the memory with Debug Module?

Also when software engineer tries to use gdb debugger, the first thing to do is loading the software elf file into memory( which sounds like DDR or other storage space to store the program)

When programmer types the keyword "load" into gdb, in my thought the RISC-V Debug Module will load the program with abstract command function to access memory.

I would glad if anyone could tackle on my thought, thanks.