Errors while generating bitstream for Rocket Chip core verilogs using vivado 2016.1

[priya dixit]

Hello all,

For mapping  a Rocket core to an FPGA

I generated synthesizable Verilog with the following commands:

$ cd $ROCKETCHIP/vsim
$ make verilog CONFIG=DefaultFPGAConfig
 

The Verilog used for the FPGA tools got generated in vsim/generated-src.

Now while generating corresponding Bitstream for the verilogs using vivado 2016.1, I am getting syntax errors:

***** Vivado v2016.1 (64-bit)
  **** SW Build 1538259 on Fri Apr  8 15:45:23 MDT 2016
  **** IP Build 1537824 on Fri Apr  8 04:28:57 MDT 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source TestHarness.tcl -notrace
create_project: Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:13 . Memory (MB): peak = 974.297 ; gain = 8.027 ; free physical = 463 ; free virtual = 4781
Command: synth_design -top TestHarness -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 8586
ERROR: [Synth 8-2715] syntax error near "DPI-C [/home/priya/rocket-chip/vsrc/SimDTM.v:3]
WARNING: [Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode [/home/priya/rocket-chip/vsrc/SimDTM.v:15]
ERROR: [Synth 8-993] bit is an unknown type [/home/priya/rocket-chip/vsrc/SimDTM.v:35]
ERROR: [Synth 8-993] bit is an unknown type [/home/priya/rocket-chip/vsrc/SimDTM.v:42]
ERROR: [Synth 8-993] int is an unknown type [/home/priya/rocket-chip/vsrc/SimDTM.v:43]
ERROR: [Synth 8-993] int is an unknown type [/home/priya/rocket-chip/vsrc/SimDTM.v:44]
ERROR: [Synth 8-993] longint is an unknown type [/home/priya/rocket-chip/vsrc/SimDTM.v:45]
ERROR: [Synth 8-993] bit is an unknown type [/home/priya/rocket-chip/vsrc/SimDTM.v:46]
ERROR: [Synth 8-993] int is an unknown type [/home/priya/rocket-chip/vsrc/SimDTM.v:47]
INFO: [Synth 8-2350] module SimDTM ignored due to previous errors [/home/priya/rocket-chip/vsrc/SimDTM.v:17]
Failed to read verilog '/home/priya/rocket-chip/vsrc/SimDTM.v'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 1 Warnings, 0 Critical Warnings and 9 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed Jan  4 15:55:27 2017...

I cloned rocket chip repository from https://github.com/ucb-bar/rocket-chip

Please help me out with the detailed steps of how to generate bitstream for rocket chip core using vivado 2016.1

Thanks for help in advance.....


Regards
Priya Dixit
IIT Madras

[xuyon...@gmail.com]

I encountered the same problem when synthesising,have you solved it ?

Thanks

yonghaoXu,

在 2017年1月4日星期三 UTC+8下午7:54:02，priya dixit写道：

[Dr Jonathan Kimmitt]

The file SimDTM.v is not meant to be used in synthesis. If you aren't interested in debugging you could replace this with an empty shell.

The reason for some of the syntax errors is that .v file are assumed to be Verilog 95 or 2K and bit is a SystemVerilog (.sv) function.

In addition DPI-C is not supported for Synthesis, you need to replace with a real hardware interface.

Furthermore Vivado 2016.1 does not correctly compile the RAM inference templates supplied with Rocket, you need to use 2018.1 or later.

Finally, if that's all too much effort, you could consult or adapt our flow at www.lowrisc.org where everything is done for you step by step.

Bearing in mind Xilinx does not support the IRLEN or USER scan chain numbers that Rocket uses by default,

you may need extra hardware if you want to do debugging and don't want to make the changes that we suggest.

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