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Correct - the 32 bit instruction set is not a subset of the 64 bit one and a binary generated for the 32 bit ISA set will in general *not* run on the 64 bit ISA.
Personally I think this is a short-sighted error.
Mike
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We support all the ISA combinations allowed by the spec except Q, and all the
legal ABI combinations where __riscv_xlen/8 == SIZEOF_LONG. Illegal ABIs are
simply when the ABI defines that arguments are passed in F register bits that
don't exist (ie, lp64d on rv64if).
Here's my attempt at creating a list, but it might be wrong. I find the
constraints easier to reason about than the list.
$ for b in rv32e rv32i rv64i; do for m in "" m; do for a in "" a; do for f in
"" f fd; do for c in "" c; do for ab in ilp32 lp64; do for af in "" $(echo $f |
cut -c1) $(echo $f | cut -c2); do echo "-march=$b$m$a$f$c -mabi=$ab$af"; done;
done; done; done; done; done; done | grep -v -e '-march=rv32e.*f' | grep -v -e
'-march=rv64.*-mabi=ilp32.*' | grep -v -e '-march=rv32.*-mabi=lp64.*' | sort |
uniq
<snip>
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git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain/riscv-gcc
contrib/download_prerequisites
cd ..
./configure --prefix=`pwd`/riscv-unknown-elf-gcc --enable-multilib
make
$ tree -d lib riscv64-unknown-elf/lib/
lib
└── gcc
└── riscv64-unknown-elf
└── 7.1.0
├── include
├── include-fixed
├── install-tools
│ └── include
├── rv32i
│ └── ilp32
├── rv32iac
│ └── ilp32
├── rv32im
│ └── ilp32
├── rv32imac
│ └── ilp32
├── rv32imafc
│ └── ilp32f
├── rv64imac
│ └── lp64
└── rv64imafdc
└── lp64d
riscv64-unknown-elf/lib/
├── ldscripts
├── rv32i
│ └── ilp32
├── rv32iac
│ └── ilp32
├── rv32im
│ └── ilp32
├── rv32imac
│ └── ilp32
├── rv32imafc
│ └── ilp32f
├── rv64imac
│ └── lp64
└── rv64imafdc
└── lp64d
36 directories
-march=rv64g
-mabi=lp64d
-mcmodel=medany
-march=rv64i
-mabi=lp64
On Thu, Jun 29, 2017 at 02:43:59PM +0200, Michael Chapman wrote:
> Correct - the 32 bit instruction set is not a subset of the 64 bit one
> and a binary generated for the 32 bit ISA set will in general *not* run
> on the 64 bit ISA.
>
> Personally I think this is a short-sighted error.
OTOH it's how it works on aarch64. AArch32 isn't a subset, and it's
not guaranteed to be present (although most current chips do have it).
On Sun, Jul 09, 2017 at 08:24:59PM +0300, Bruce Hoult wrote:
> On Sun, Jul 9, 2017 at 1:37 PM, Richard W.M. Jones <rjo...@redhat.com>
> wrote:
>
> > On Thu, Jun 29, 2017 at 02:43:59PM +0200, Michael Chapman wrote:
> > > Correct - the 32 bit instruction set is not a subset of the 64 bit one
> > > and a binary generated for the 32 bit ISA set will in general *not* run
> > > on the 64 bit ISA.
> > >
> > > Personally I think this is a short-sighted error.
> >
> > OTOH it's how it works on aarch64. AArch32 isn't a subset, and it's
> > not guaranteed to be present (although most current chips do have it).
> >
>
> Not really a great example, as the instruction sets are totally different.
You omitted the rest of my message which contains my central point.
What is running 32 bit instructions good for, which cannot be achieved
by using virtualization or emulation?
> I agree with Michael Chapman that this incompatibility is unfortunate, short sighted, and perhaps even worse: gains no advantage.
>
RVC decodes the same opcodes to different instructions based on RV32 vs RV64 vs RV128 (JAL vs ADDIW, FSW vs SD, etc.). So maintaining compatibility would mean a suffering of code compression for 2 out of the 3 architectures. Then the knives come out to decide which of the three should be favored.
There are some other subtle reasons that make the RV32-is-a-subset a Siren Song, and a previous mailing list thread briefly discusses this:
https://groups.google.com/a/groups.riscv.org/forum/#!searchin/isa-dev/subset/isa-dev/cqtEfUI6BPQ/TqVx9Z44BgAJ
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