writing inline assembly in C code for RISCV assembler

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muralihegde100

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Mar 15, 2021, 4:38:47 AM3/15/21
to RISC-V SW Dev
Hi,

Currently i created a new custom instruction for RISCV in RISCV gnu toolchain by modifying the assembler. The instruction structure looks like below

{"my_custom_insn",    0,  INSN_CLASS_I, "s,t,w",  MATCH_CUSTOM_INSN, MASK_CUSTOM_INSN, match_opcode, 0},

s->RS1
t->RS2
w-> this is an immediate value passed as constant in the instruction. argument 'w' is basically 2 bits (bit 30..31). Argument 'w' is already added as assembler state machine logic in the function 
 "validate_riscv_insn" of assembler.

Now Ex. i want to write instruction as my_custom_insn rs1, rs2, 10, where 10 is like immediate value.

This is basically encoded as "R" type instruction (register to register).  basically "rd " is encoded as 0 and rs1 itself is used as destination.

How should i write inline assembly of this instruction in C code?

I have attached a document which explains the encoding format of the instruction which i designed.
instruction_encodingt.docx

Sober Liu

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Mar 16, 2021, 1:16:11 AM3/16/21
to muralihegde100, RISC-V SW Dev

For GNU toolchain, the inline assembler is independent with instruction encoding.

If you can use this instruction in .S file, then you can use it as inline C.

 

E.g., for asm volatile (“insn_x, %0, %1 %2” : “=r”(x1) : “m”(x2), “I”(0));

the “insn_x, %0, %1 %2” is just a format string like printf has. And Gcc manual describes the way to replace place holder %<idx> from arguments.

From another side, the argument list is the interface with normal C, for dependency and register share.

 

Regards.

 

From: muralihegde100 <hegde...@gmail.com>
Sent: 2021315 16:39
To: RISC-V SW Dev <sw-...@groups.riscv.org>
Subject: [sw-dev] writing inline assembly in C code for RISCV assembler

 

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MK Kim

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Mar 16, 2021, 1:18:54 AM3/16/21
to Sober Liu, muralihegde100, RISC-V SW Dev
Hello All, 
I'm MK nice to meet you.

Additionally i have one question. 

I want to use inline assembly for RISCV 

ARM has it as below
for loop
b .
Is there b assembler in RiscV ? does it know anyone? 

BR,
MK

Sober Liu

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Mar 16, 2021, 2:07:12 AM3/16/21
to MK Kim, muralihegde100, RISC-V SW Dev
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