[PLIC] Interrupt does not occur when disabling in the ISR before complete

[Padmarao Begari]

Hi,

Point 1 - The Interrupt is not working

Point 2 - The Interrupt is working 

1). The Interrupt does not occur when disabling the interrupt before interrupt complete, Is this expected behaviour with the PLIC?

With below Pseudo code, Claim the interrupt number and a call to the handler, the interrupt is disabled in the handler and  there is no

impact on the Interrupt Complete register when writing with the interrupt number, so the next interrupt(same) doesn't occur even

though the interrupt is enabled.

***********************PLIC External Interrupt ISR Pseudo Code*********************************

void handle_m_ext_interrupt(void) {     int_num = PLIC_ClaimIRQ();      /* get interrupt number by reading interrupt claim register */     ext_irq_handler(int_num);       /* service the interrupt handler */     PLIC_CompleteIRQ(int_num); /* Clear interrupt claim/complete register */     PLIC_EnableIRQ(int_num);  /* enable interrupt  here or later */ } void  ext_irq_handler(int_num) {     PLIC_DisableIRQ(int_num);  /* disable interrupt */ }

***************************************************************************************************

2). The Interrupt occurs when the interrupt complete is cleared before disable the interrupt and getting the next interrupt.

***********************PLIC External Interrupt ISR Pseudo Code*********************************

void handle_m_ext_interrupt(void) {     int_num = PLIC_ClaimIRQ();      /* get interrupt number by reading interrupt claim register */     ext_irq_handler(int_num);       /* service the interrupt service handler */     PLIC_EnableIRQ(int_num); /* enable interrupt  here or later */ } void  ext_irq_handler(int_num) {     PLIC_CompleteIRQ(int_num); /* Clear interrupt claim/complete register */     PLIC_DisableIRQ(int_num);  /* disable interrupt */ }

************************************************************************************

Regards Padmarao

[Richard Herveille]

Is this comment for the PLIC in general or a particular implementation?

 

Cheers,

Richard

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[Padmarao Begari]

It’s SiFive PLIC

On 07-Mar-2023, at 9:40 PM, Richard Herveille <richard....@roalogic.com> wrote:



[Richard Herveille]

I can’t help you with that one. 

We have our own implementation: https://github.com/roalogic/plic

The user guide/datasheet describes how we think the ISR should work. 

Richard 

On Mar 7, 2023, at 08:21, Padmarao Begari <padma...@gmail.com> wrote:

 It’s SiFive PLIC

[Jun Xie]

https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#:~:text=If%20the%20completion%20ID%20does%20not%20match%20an%20interrupt%20source%20that%20is%20currently%20enabled%20for%20the%20target%2C%20the%20completion%20is%20silently%20ignored.

It seems that the behavior you described meets the requirements of spec.

[Sebastian Huber]

Where is it specified in

https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-completion

that the interrupt completion depends on the enabled/disabled state of the interrupt?

For example, the described behaviour is not implemented in the Qemu PLIC emulation:

https://github.com/qemu/qemu/blob/master/hw/intc/sifive_plic.c#L242

In fact, the described behaviour is quite unusual for an interrupt controller. The Arm GIC, NXP MPIC, and Gaisler IRQ(A)MP for example work differently.

How can you safely implement a two step interrupt processing (interrupt context followed by task context) which the PLIC?

[Jun Xie]

The last sentence of the first paragraph of Chapter 8 says “If the completion ID does not match an interrupt source that is currently enabled for the target, the completion is silently ignored.”

I think it means that the interrupt can only be completed when the interrupt is enabled.

In addition, I thought the intention of the PLIC is to mask/unmask requests from external interrupt sources through claim/complete, so there is no need to enable/disable interrupts in runtime. What's the purpose of disabling interrupt here?