4-byte instructions may begin on any 2-byte boundary when the
Compressed extension is present, so odd-length sequences of 2-byte
instructions are legal.
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Thanks :-)
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BTW - did you see this?
- https://gcc.gnu.org/ml/gcc/2018-05/msg00012.html
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Interesting.. am also interested to know if there are any special code density optimization options in gcc for riscv-target.
On 14 May 2018 at 06:55, Bruce Hoult <br...@hoult.org> wrote:
BTW - did you see this?
- https://gcc.gnu.org/ml/gcc/2018-05/msg00012.htmlI hadn't seen it. Interesting.I see they claim 20% denser code than previous MIPS, but only 10% denser compared to competitors (presumably Thumb2).I didn't find the detailed instruction set, but it sounds as if a number of instructions are going to expand to multiple uops (or hardware sequencing).
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Only a static order of register allocation at the moment. Much work could be done given the manpower and no higher priorities.
On Mon, May 14, 2018 at 5:21 PM, Gnanasekar R <gnanase...@gmail.com> wrote:
Interesting.. am also interested to know if there are any special code density optimization options in gcc for riscv-target.--On 14 May 2018 at 06:55, Bruce Hoult <br...@hoult.org> wrote:--BTW - did you see this?
- https://gcc.gnu.org/ml/gcc/2018-05/msg00012.htmlI hadn't seen it. Interesting.I see they claim 20% denser code than previous MIPS, but only 10% denser compared to competitors (presumably Thumb2).I didn't find the detailed instruction set, but it sounds as if a number of instructions are going to expand to multiple uops (or hardware sequencing).
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