How to disable compression

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Nhon Quach

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Dec 19, 2017, 7:54:27 PM12/19/17
to sw-...@groups.riscv.org
Hi all,

Is there an assembly switch or a way that will allow me to prevent the RISCV assembler from generating compressed code?  If there is such a switch/way, do I still need to stay away from the compressed opcode in my assembler code? I am coding in assembly language.

Thanks,

Nhon

Jim Wilson

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Dec 19, 2017, 8:02:39 PM12/19/17
to Nhon Quach, RISC-V SW Dev
You can use -march and pass in an architecture that does not support
compressed instructions. Or you can put ".option norvc" in an
assembler source file to turn off compression. If you use a
compressed opcode, and compressed instructions are turned off, then
you will get an assembler error.

Jim

Vasan VS

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Dec 20, 2017, 12:58:50 AM12/20/17
to Nhon Quach, sw-...@groups.riscv.org
You can use the --march options to be RV64IMAFD for your toolchain to be generated with non CISA of RISCV. 

Best wishes

Vasan 

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