FireSim now open-sourced!
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Sagar Karandikar
May 21, 2018, 1:15:46 PM5/21/18
to RISC-V HW Dev, RISC-V SW Dev, fir...@googlegroups.com, David Biancolin, Howard Mao, Donggyu Kim, Alon Amid, Krste Asanovic
We’re excited to announce that FireSim is now open-sourced! FireSim enables cycle-accurate FPGA-accelerated simulation of Rocket Chip-based systems on Amazon EC2 F1 at 10s to 100s of MHz depending on simulation scale (e.g. ~150 MHz for a single quad-core Rocket Chip, ~10 MHz for a 1024-node, 4096-core networked datacenter of Rocket Chips with an aggregate of 16 TB of memory).
You can find the FireSim release here: https://github.com/firesim/firesim.
We’ve written extensive documentation, which you can find here: https://docs.fires.im.
In this release, we support 2 use cases:
1) Parallel single-node simulation: This simulates many Rocket Chips in parallel (without a simulated network) to support running large single-node benchmark suites. For example, since SPECInt 2017 with reference inputs consists of several individual long-running benchmarks, we can run them in parallel and collect cycle-accurate performance results for the full reference inputs in ~1 day, automatically (see our docs for running SPEC: https://docs.fires.im/en/latest/Advanced-Usage/Workloads/SPEC-2017.html).
2) Datacenter/cluster simulation: Here, we can simulate datacenters of Rocket Chips (e.g. 1024 Rocket Chip nodes) interconnected by an Ethernet network, with cycle-accuracy. This use case is detailed in our paper to appear at ISCA 2018 (preprint: https://sagark.org/assets/pubs/firesim-isca2018.pdf, lightning talk: https://www.youtube.com/watch?v=4XwoSe5c8lY). We include scripts and documentation in our public release that allow users to reproduce the graphs in this paper automatically (see the docs: https://docs.fires.im/en/latest/Advanced-Usage/Workloads/ISCA-2018-Experiments.html).
We have a FireSim-specific mailing list (CC'd), which you can join here: https://groups.google.com/forum/#!forum/firesim. You can also follow our Twitter account, https://twitter.com/firesimproject, to get project updates.
Lastly, if you’re a researcher, you can apply to get free AWS credits from Amazon: https://aws.amazon.com/grants/.
We’re using this infrastructure for our own research at Berkeley, so we’ll be continually adding features -- we welcome issues and pull-requests!
-Sagar
Muhammad Ali Akhtar
May 21, 2018, 3:03:38 PM5/21/18
to Sagar Karandikar, RISC-V HW Dev, RISC-V SW Dev, fir...@googlegroups.com, David Biancolin, Howard Mao, Donggyu Kim, Alon Amid, Krste Asanovic
Correct me If I am wrong.
Firesim is something similar to GEM5? The difference is GEM5 runs purely on x86 host without using any FPGA acceleration, (thats why GEM5 simulation are slow i.e. KIPS) and Firesim uses FPGA accelerators on Amazon F1 to speed up the simulation speed
Am I right?
Secondly, Firesim currently only supports Rocket and doesn't support other ISAs (x86, arm) like gem5.
My apologies if the questions / comments are too trivial or complete nonsense. I am a beginner.
Firesim is something similar to GEM5? The difference is GEM5 runs purely on x86 host without using any FPGA acceleration, (thats why GEM5 simulation are slow i.e. KIPS) and Firesim uses FPGA accelerators on Amazon F1 to speed up the simulation speed
Am I right?
Secondly, Firesim currently only supports Rocket and doesn't support other ISAs (x86, arm) like gem5.
My apologies if the questions / comments are too trivial or complete nonsense. I am a beginner.
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Sagar Karandikar
May 21, 2018, 8:16:53 PM5/21/18
to muhamma...@gmail.com, RISC-V HW Dev, RISC-V SW Dev, fir...@googlegroups.com, David Biancolin, Howard Mao, Donggyu Kim, Alon Amid, Krste Asanovic
The end goal is similar to gem5 - ultimately we want to collect performance results for some hardware design - but the approaches are different.
In FireSim, the simulator is automatically derived from the RTL that describes a hardware design, in this case Rocket Chip (although the methodology is not specific to Rocket Chip). So the simulator "implements" the RISC-V ISA as an artifact of the fact that it is modeling Rocket Cores (that implement RISC-V) on the FPGA. Similarly, we can plug-in "BOOM Chips" and model those without extra effort, since the simulation is derived from the RTL (this is a WIP, should show up on a branch soon).
With our automation, we're aiming to achieve the ease-of-use of gem5, but with the performance of FPGA-accelerated simulation, all while being derived from real hardware implementations rather than handwritten abstract-models.
-Sagar
On Mon, May 21, 2018 at 12:03 PM Muhammad Ali Akhtar <muhamma...@gmail.com> wrote:
Correct me If I am wrong.
Firesim is something similar to GEM5? The difference is GEM5 runs purely on x86 host without using any FPGA acceleration, (thats why GEM5 simulation are slow i.e. KIPS) and Firesim uses FPGA accelerators on Amazon F1 to speed up the simulation speed
Am I right?
Secondly, Firesim currently only supports Rocket and doesn't support other ISAs (x86, arm) like gem5.
My apologies if the questions / comments are too trivial or complete nonsense. I am a beginner.
On Mon, May 21, 2018 at 10:15 PM, Sagar Karandikar <sag...@eecs.berkeley.edu> wrote:
We’re excited to announce that FireSim is now open-sourced! FireSim enables cycle-accurate FPGA-accelerated simulation of Rocket Chip-based systems on Amazon EC2 F1 at 10s to 100s of MHz depending on simulation scale (e.g. ~150 MHz for a single quad-core Rocket Chip, ~10 MHz for a 1024-node, 4096-core networked datacenter of Rocket Chips with an aggregate of 16 TB of memory).You can find the FireSim release here: https://github.com/firesim/firesim.We’ve written extensive documentation, which you can find here: https://docs.fires.im.In this release, we support 2 use cases:1) Parallel single-node simulation: This simulates many Rocket Chips in parallel (without a simulated network) to support running large single-node benchmark suites. For example, since SPECInt 2017 with reference inputs consists of several individual long-running benchmarks, we can run them in parallel and collect cycle-accurate performance results for the full reference inputs in ~1 day, automatically (see our docs for running SPEC: https://docs.fires.im/en/latest/Advanced-Usage/Workloads/SPEC-2017.html).2) Datacenter/cluster simulation: Here, we can simulate datacenters of Rocket Chips (e.g. 1024 Rocket Chip nodes) interconnected by an Ethernet network, with cycle-accuracy. This use case is detailed in our paper to appear at ISCA 2018 (preprint: https://sagark.org/assets/pubs/firesim-isca2018.pdf, lightning talk: https://www.youtube.com/watch?v=4XwoSe5c8lY). We include scripts and documentation in our public release that allow users to reproduce the graphs in this paper automatically (see the docs: https://docs.fires.im/en/latest/Advanced-Usage/Workloads/ISCA-2018-Experiments.html).We have a FireSim-specific mailing list (CC'd), which you can join here: https://groups.google.com/forum/#!forum/firesim. You can also follow our Twitter account, https://twitter.com/firesimproject, to get project updates.Lastly, if you’re a researcher, you can apply to get free AWS credits from Amazon: https://aws.amazon.com/grants/.We’re using this infrastructure for our own research at Berkeley, so we’ll be continually adding features -- we welcome issues and pull-requests!-Sagar
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Muhammad Ali Akhtar
May 22, 2018, 5:15:20 AM5/22/18
to Sagar Karandikar, RISC-V HW Dev, RISC-V SW Dev, fir...@googlegroups.com, David Biancolin, Howard Mao, Donggyu Kim, Alon Amid, Krste Asanovic
Sagar,
Thanks a lot for your response. Another quick question. as far as I know, both Rocket and Boom implement standard ISA and don't include any custom extension. If I add a custom extension / accelerator in my chisel code and than generate RTL, Firesim will automatically be able to derive the custom ISA from RTL and simulate it right?
Thanks a lot for your response. Another quick question. as far as I know, both Rocket and Boom implement standard ISA and don't include any custom extension. If I add a custom extension / accelerator in my chisel code and than generate RTL, Firesim will automatically be able to derive the custom ISA from RTL and simulate it right?
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Sagar Karandikar
May 22, 2018, 1:10:24 PM5/22/18
to Muhammad Akhtar, RISC-V HW Dev, RISC-V SW Dev, fir...@googlegroups.com, David Biancolin, Howard Mao, Donggyu Kim, Alon Amid, Krste Asanovic
That's right, if you add an accelerator in Rocket Chip (or really, any arbitrary Chisel RTL modifications), it will be automatically included in the simulated target by FireSim. Then, you can run software (with the custom instructions) on it as you would if you had the real silicon. Adding your own devices to the simulated system works similarly and we have a tutorial for it: https://docs.fires.im/en/latest/Developing-New-Devices/index.html
-Sagar
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