gcc extended asm compressed register constraint

[josema...@gmail.com]

I'm wondering if there is an extended asm constraint (can't find it in gcc's docs) for specifying the subset of registers allowed on C extension instructions. I want be able to define a function to inline a compressed load/store. For example:

static inline void c_sd(uintptr_t addr, uint64_t value){

    asm volatile(

        "c.sd %0, 0(%1)\n\t"

        :: "?"(value), "?"(addr): "memory"

    );

}

Jose

[Tommy Murphy]

Does gcc extended inline asm help at all?

https://gcc.gnu.org/onlinedocs/gcc/Using-Assembly-Language-with-C.html#Using-Assembly-Language-with-C

---

From: josema...@gmail.com <josema...@gmail.com>
Sent: Saturday, August 7, 2021 8:03:14 PM
To: RISC-V SW Dev <sw-...@groups.riscv.org>
Subject: [sw-dev] gcc extended asm compressed register constraint

 

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[Jose Martins]

Hey Tommy, thanks for replying. I don't know if I understood your point, but inline asm was exactly what I was referring to. Specifically, I was looking for a RISC-V specific way to constraint a register field to the compressed extension registers. There are similar constraints, for example, for csr instruction immediates: https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints 

[Michael Chapman]

There is no such constraint in GCC at the moment.
However, it is very easy to add.

Mike

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[Jose Martins]

Thanks Mike. I'll just force specific registers and add them to the clobber list.