RV32E support for GNU toolchain/Qemu

[Kito Cheng]

Hi folks:

I'd like to announce the RV32E support is coming for GNU toolchain and
Qemu, it's under review on github, any comments or suggestion are
welcome :)

GCC: https://github.com/riscv/riscv-gcc/pull/77
Binutils: https://github.com/riscv/riscv-binutils-gdb/pull/87
newlib: https://github.com/riscv/riscv-newlib/pull/18
Qemu: https://github.com/riscv/riscv-qemu/pull/61

[Michael Clark]

Hi Kito,

I vaguely remember seeing the use of t3 in the PLT and didn't see a change to the PLT in binutils. Maybe it was changed already. Does the binutils change make the unavailable registers emit errors so the test will pick up any code that emits registers >15?

Sure it's like RV32E is static however the PLT can be made to work (assuming it still uses t3).

Michael

P.S. Andrew's strict operands change in binutils took this approach and helped us find a case where gcc wasn't emitting the strict ISA manual subset of instructions, due to the strict checking in the assembler. The same can be done for RV32E registers I guess.

Sent from my iPhone

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[Kito Cheng]

Hi Michael:

Thanks for your review,

For PLT issue: yes , PLT still using t3 to make PLT header and entry,
it's make RV32E can't generate correct PIC/PIE code in bare metal
environment now.

For reg > 15: Binutils have check register is valid for RV32E during
assemble time[1].

[1] https://github.com/riscv/riscv-binutils-gdb/pull/87/commits/2614e831bf99f53a2a0334204106c271db0d7049#diff-a04ecfdef25a06707d80c9e120cb4edbL442

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