Hi,
I'm a final-year student working on my undergraduate thesis related to the RISC-V Packed SIMD P extension.
I'm currently studying the draft specification "Preliminary in-progress RISC-V P Extension Version 0.12-draft (2026-03-08)" and trying to build a small experimental environment to understand and test some of the instructions.
I would like to ask:
Is there any Spike, Sail, or QEMU implementation that supports the P extension?
If not, what would be the recommended starting point to prototype these instructions?
Is modifying Spike decode tables and instruction semantics a reasonable approach for experimentation?
My goal is only to run small test programs and study the behavior of packed SIMD instructions for my thesis.
Any suggestions or references would be greatly appreciated.
Thanks.
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Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.Hi Rich,
Thanks for the pointer.
Hi Jiawei, if you're on this thread, I would really appreciate any insights you might have regarding experimentation with the RISC-V P extension.
Best regards,
-Thang
Hi Jiawei,
Thank you for your response and for sharing the QEMU implementation.
I noticed that in the QEMU repository (dev-p-018 branch) the P extension seems to follow version 0.18. However, when I checked the RISC-V P extension specification at https://github.com/riscv/riscv-p-spec, the latest version I could find is v0.12.
Could you please let me know where I can find the specification for version 0.18, or if there is a draft available somewhere?
Thank you very much for your help.
Best regards,
Thang
Hi Tang,
We have implemented the QEMU supports for P extension.
You can check it in https://github.com/mollybuild/qemu/tree/dev-p-018
Since I'm not an expert for simulator part, maybe you can ask the committer in QEMU repo.
Best,
Jiawei
Hi Tang,
Sorry for not explain the version clearly, the QEMU is implemented based on John Hauser's document https://www.jhauser.us/RISCV/ext-P/
And RISC-V P extension specification at github https://github.com/riscv/riscv-p-spec is also base form John Hauser's document.
The encoding and description are the same but github version is using ascii for review.
BR,
Jiawei
Hi Jiawei, hi everyone,
Following the previous discussion, I am trying to build a RISC-V GNU toolchain with P-extension (Packed SIMD) support for small experiments.
However, the build fails during the GCC stage with an internal compiler error.
Error
<built-in>: internal compiler error: in c_builtin_function, at c/c-decl.cc:4916
0x2f82966 internal_error(char const*, ...)
make[2]: *** [gcc/c/Make-lang.in:152: s-selftest-c] Error 1
make[1]: *** [Makefile:4713: all-gcc] Error 2
make: *** [Makefile:654: stamps/build-gcc-newlib-stage1] Error 2
Host system
OS: Ubuntu 22.04.5 LTS (jammy)
Kernel: Linux 6.8.0-101-generic
Architecture: x86_64
Host compiler:
gcc 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04.3)
g++ 11.4.0
P-extension repositories used
According to the README of the RISC-V P-extension specification:
P-extension spec: https://github.com/riscv/riscv-p-spec
Toolchain components used:
GCC (p-dev branch) v0.18 gcc:https://github.com/ruyisdk/riscv-gcc/tree/p-dev
Binutils (p-dev branch) v0.18 binutils: https://github.com/ruyisdk/riscv-binutils/tree/p-dev
GNU toolchain repositories tested
I tried several toolchain bases:
git clone https://github.com/riscv-collab/riscv-gnu-toolchain.git
git clone https://github.com/TelGome/riscv-gnu-toolchain.git
git clone https://github.com/pz9115/riscv-gnu-toolchain.git
Configure command
../configure \
--prefix=/home/thang/Workspace/01_Verify/tools/riscv-p-toolchain2 \
--with-arch=rv32im \
--with-abi=ilp32 \
--with-gcc-src=$(pwd)/../riscv-gcc-p \
--with-binutils-src=$(pwd)/../riscv-binutils-p
I also tried:
--with-arch=rv32imp
Build command
make -j3 --output-sync=target 2>&1 | tee build.log
Questions
Any guidance or references would be greatly appreciated.
Best regards,
Thang