Cycle approximate simulation

[Rajeev Kumar]

Hi, 

I m trying to run a simple program in RISCV assembly let's say add 10 numbers.

now i want to know how much cycle each instruction takes .

I m trying to run this in Imperass with the following command 

 

To create the object file

corev-openhw-gcc-centos7-20230223/bin/riscv32-corev-elf-as   -march rv32im_zca_zcb_zcmp_zcmt_zba_zbb_zbc_zbs -o add.o  add.S

 

To create the elf file from the object file

 

   /work/rakumar/corev-openhw-gcc-centos7-20230223/bin/riscv32-corev-elf-ld -o  add.elf  add  .o

 

To run the ISS with gdb

/tool/imperas_dev/20220901/bin/Linux64/iss.exe -processorfile /tool/imperas_dev/20220901/lib/Linux64/ImperasLib/openhwgroup.ovpworld.org/processor/riscv/1.0/model.so -variant CV32E40X --verbose --trace -program  add.elf -gdbconsole -gdbpath /tool/gcc/riscv32-embecosm-gcc-centos7-20211031/bin/riscv32-unknown-elf-gdb

Simulated time i got it but i want to know how much each instructions take.

Is there some way to find the no of cycles and how much each instruction takes 

in Imperass simulator 

Thanks 

rajeev

[Tommy Murphy]

https://www.ovpworld.org/about_faq

Can OVP add cycle accurate (approximate) simulation capability?

There are currently no plans to add cycle accurate simulation capability to OVP modeling APIs or OVPsim. It is possible to do so, and could happen in the future. OVP is focused on Instruction Accurate - if you need cycle approximate simulation, then please contact a commercial vendor such as Imperas.

---

From: Rajeev Kumar <rajeevr...@gmail.com>
Sent: Friday, April 14, 2023 9:38:15 AM
To: RISC-V ISA Dev <isa...@groups.riscv.org>
Subject: [isa-dev] Cycle approximate simulation

 

--
You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/ff83a508-24e5-470d-be39-4d93a4fa14d3n%40groups.riscv.org.

[Rajeev Kumar]

Any guide on : how to add those 

[Tommy Murphy]

I suspect that it's not trivial to add cycle accuracy to OVPsim.

There exist other RISC-V cycle accurate simulators.

It's not difficult to find info about them by searching.

---

From: Rajeev Kumar <rajeevr...@gmail.com>
Sent: Friday, April 14, 2023 12:07:55 PM

To: RISC-V ISA Dev <isa...@groups.riscv.org>

Cc: Tommy Murphy <tommy_...@hotmail.com>; Rajeev Kumar <rajeevr...@gmail.com>
Subject: Re: [isa-dev] Cycle approximate simulation

 

[MitchAlsup]

Cycle accurate to who's RISC-V microArchitecture ??

a) 1-wide

b) 1-wide with compressed instructions

c) 1-wide with compressed instructions and instruction-fusion

d) 4-Wide Out-of-Order

e) 8-wide Out-of-Order

How big are the caches

How many layers of caches

What is the latency to DRAM

What kind of DRAM controller is in use

.....

Does this include excursions through the OS so you can simulate exceptions and interrupts ??

Does this include simulated devices so you can test device drivers ??

....

It is no wonder why it is hard to answer your question.

[Mark Hill]

Hi Rajeev,

 

If you are interested in CA models I would suggest joining the Performance Modelling SIG (https://lists.riscv.org/g/sig-perf-modeling).

 

You can find its charter here:

 

https://github.com/riscv-admin/perf-modeling/blob/main/CHARTER.md

 

Regards,

Mark

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/5cbfec45-e2b8-4108-9fc7-735129f9aa28n%40groups.riscv.org.