another intel "optimisation"

[Luke Kenneth Casson Leighton]

https://betanews.com/2018/06/14/floating-point-lazy-state-save-restore-vulnerability/
https://it.slashdot.org/story/18/06/14/1553255/another-day-another-intel-cpu-security-hole-lazy-state#comments

this is a particularly fascinating comment:
https://it.slashdot.org/comments.pl?sid=12234158&cid=56784002

soo.. anyone thinking of implementing lazy context-switch save/restore
in a RISC-V implementation? :)

l.

[Jacob Lifshay]

I think Intel's problems are not caused by their optimizations, but by speculating past everything that they shouldn't.

Jacob Lifshay

--
You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org.
To post to this group, send email to isa...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/isa-dev/.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CAPweEDyYZQ%3D%3DOXoCcr40e7L%3DCz2Mh%3DZeyF1V%3D98w6wVT9DJMGg%40mail.gmail.com.

[Brady O'Brien]

The privileged spec does support lazy context-switching for the FPU. See the FS and XS fields of mstatus.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CAC2bXD5im-DcBd%3DWm_qFoOz3t8XWDdVaUkHWbb_JG4Ct%2BC_oag%40mail.gmail.com.

[Alex Elsayed]

The problem here is not lazy switching; it's that a Spectre-style attack can leak information that is in disabled functional units and register files.

Disabling lazy switching is the kludgy, oversized hammer that is being used to work around the more fundamental brokenness.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CAC_mAiixO5JaBMoXXv%3DSKtt4xwf%3DqR8dz2j2-RxiqRAHmXasWA%40mail.gmail.com.